Method and apparatus for data transfer between at least two modules interconnected by a serial data bus
View Patent ↗Method and apparatus for serial data transfer between at least two modules ( 10, 12 ) connected to each other by way of a serial data bus ( 18 ) where the data transfer is governed by a clock signal (CLK). The modules ( 10, 12 ) each comprise a receiver unit ( 30 ) for the reception of the data and a transmitter unit ( 22 ) for the transmission of data. The output of a data value by the transmitter unit ( 22 ) of one module ( 12 ) to another module ( 10 ) at the serial data bus ( 18 ), and the import of the data value by the receiver unit ( 30 ) of the corresponding other module ( 10 ) are initiated by slopes of the clock signal (CLK). The clock signal that triggers the transmission of this data value in the one module ( 12 ) is delayed via a delay element ( 38 ) one pulse repetition period (ΔTP) of the clock signal (CLK).
1. A method for the transfer of data between a first module and a second module connected to each other by a serial data bus under the control of a clock signal, whereby each module comprises a receiver unit for the reception of the data and a transmitter unit for the transmission of data, and where the output of a data value by the transmitter unit of one module and the import of the data value into the receiver unit of the corresponding other module is initiated by clock signal slopes, comprising the steps of:
supplying the clock signal from the first module ( 10 ) to the second module ( 12 ) via a clock line;
triggering transmission of a data value ( 22 ) from the second module upon a first predetermined clock signal slope of the clock signal;
delaying at the first module ( 10 ) the clock signal that triggers the transmission of a data value from the second module ( 12 ) by one pulse repetition period; and
importing the data value in the first module ( 10 ) upon a second predetermined clock slope of the delayed clock signal.
2. A serial data interface for data transmission comprising:
a serial data bus ( 18 ) connecting a first module and a second module;
a clock generator (A) disposed in said second module generating a clock signal;
a clock line ( 18 ) supplying said clock signal from said second module to said first module;
a transmitter unit ( 22 ) disposed in said first module ( 12 ) receiving said clock signal via said clock line and connected to said serial data bus, said transmitter unit ( 22 ) transmitting a bit of serial data via a serial data bus upon a predetermined clock edge of said clock signal;
a delay element ( 38 ) disposed in said second module ( 10 ) receiving said clock signal from said clock generator, said delay element ( 38 ) delaying said clock signal one pulse repetition period thereby forming a delayed clock signal; and
a receiver unit ( 30 ) disposed in said second module ( 10 ) and connected to said serial data bus ( 18 ) and said delay element ( 38 ), said receiver unit ( 30 ) importing a bit of serial data from said serial data bus upon said predetermined clock edge of said delayed clock signal.
3. The serial data interface of claim 2 , wherein:
said transmitter unit ( 22 ) includes a register having a serial output connected to said serial data bus.
4. The serial data interface of claim 2 , wherein:
said receiver unit ( 30 ) includes a register having a serial input connected to said serial data bus.
5. The serial data interface of claim 2 , wherein:
said first module ( 12 ) is a slave unit; and
said second module ( 10 ) is a master unit and includes said delay element ( 39 ) and a clock generator (CLK) .