Methods and apparatus for managing probe requests
View Patent ↗According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for reducing the number of transactions in a multiple cluster system are provided. In one example, memory controller filter information is used to probe a request or remote cluster while bypassing a home cluster memory controller.
1. A computer system, comprising:
a home cluster including a first plurality of processors and a home cache coherence controller, the first plurality of processors and the home cache coherence controller interconnected in a point-to-point architecture;
wherein the home cache coherence controller is configured to receive a probe request and determine if the probe request should bypass a memory controller associated with the home cluster, wherein the memory controller is bypassed by forwarding the probe directly to a remote cluster from the home cluster cache coherence controller, the remote cluster comprising a second plurality of processors interconnected in a point-to-point architecture.
2. The computer system of claim 1 , wherein the probe request is associated with a particular memory line.
3. The computer system of claim 2 , wherein the cache coherence controller is further configured to block subsequent probe requests associated with the particular memory line until a transaction complete indicator is received from a request cluster.
4. The computer system of claim 3 , wherein the transaction complete indicator is a source done message from the home cache coherence controller.
5. The computer system of claim 1 , wherein the home cache coherence controller is configured to determine if the probe request should bypass the memory controller by identifying characteristics associated with the probe request.
6. The computer system of claim 5 , wherein the probe request should bypass the memory controller if a memory line associated with the probe request is in the modified state.
7. The computer system of claim 6 , wherein the probe request should bypass the memory controller if a memory line associated with the probe request is in the owned state and the probe request is a read request.
8. The computer system of claim 7 , wherein the probe request should not bypass the memory controller if a memory line associated with the probe request is in the invalid or shared states.
9. The computer system of claim 7 , wherein the probe request should not bypass the memory controller if a memory line associated with the probe request is in the owned state and the probe request is a read/write request.
10. The computer system of claim 7 , wherein the home cache coherence controller determines that the probe request should bypass the memory controller by using memory controller filter information associated with a cache coherence directory.
11. The computer system of claim 10 , wherein the cache coherence directory identifies the state of a plurality of memory lines.
12. The computer system of claim 11 , wherein the characteristics associated with the probe request include whether the probe request is a read or a read/write request.
13. A method for managing probes, the method comprising:
receiving a probe request at a home cache coherence controller in a home cluster, the home cluster including a first plurality of processors and the home cache coherence controller, the first plurality of processors and the home cache coherence controller interconnected in a point-to-point architecture;
determining if the probe request should bypass a memory controller associated with the home cluster, wherein the memory controller is bypassed by forwarding the probe directly to a remote cluster from the home cluster cache coherence controller, the remote cluster comprising a second plurality of processors interconnected in a point-to-point architecture.
14. The method of claim 13 , wherein the probe request is associated with a particular memory line.
15. The method of claim 14 , wherein cache coherence controller is further configured to block subsequent probe requests associated with the particular memory line until a transaction complete indicator is received from a request cluster.
16. The method of claim 15 , wherein the transaction complete indicator is a source done message from the home cache coherence controller.
17. An apparatus for managing probes, the apparatus comprising:
means for receiving a probe request at a home cache coherence controller in a home cluster, the home cluster including a first plurality of processors and the home cache coherence controller, the first plurality of processors and the home cache coherence controller interconnected in a point-to-point architecture;
means for determining if the probe request should bypass a memory controller associated with the home cluster, wherein the memory controller is bypassed by forwarding the probe directly to a remote cluster from the home cluster cache coherence controller, the remote cluster comprising a second plurality of processors interconnected in a point-to-point architecture.
18. The apparatus of claim 17 , wherein the probe request is associated with a particular memory line.
19. The apparatus of claim 18 , wherein cache coherence controller is further configured to block subsequent probe requests associated with the particular memory line until a transaction complete indicator is received from a request cluster.
20. The apparatus of claim 19 , wherein the transaction complete indicator is a source done message from the home cache coherence controller.