Chip-scale schottky device
View Patent ↗A chip-scale schottky package which has at least one cathode electrode and at least one anode electrode disposed on only one major surface of a die, and solder bumps connected to the electrode for surface mounting of the package on a circuit board.
1. A semiconductor device package comprising:
a semiconductor die having a first major surface;
a schottky barrier structure connected to a portion of said first major surface;
a first electrode electrically connected to said schottky barrier structure;
a second electrode electrically connected to said first major surface of said semiconductor die, but spaced from said first electrode;
a plurality of solder bumps at least one of which is connected to one said first electrode and said second electrode; and
a guard ring formed in said semiconductor die in a region at least partly between said first electrode and said second electrodes wherein said first electrode surrounds said second electrode, and wherein said semiconductor die includes a first lightly doped portion and a second highly doped portion, said first lightly doped portion being disposed over said second highly doped portion, and further comprising a sinker extending from a major surface of said first lightly doped portion to said second highly doped portion, wherein said second electrode is electrically connected to said sinker.
2. A semiconductor device package according to claim 1 , further comprising a passivation layer disposed over said first electrode and said second electrode, wherein said plurality of solder bumps are disposed over a free surface of said passivation layer and extend through openings in said passivation layer to said first and second electrodes.
3. A semiconductor device package according to claim 1 , wherein said guard ring is around the periphery of said second electrode.
4. A semiconductor device package comprising:
a semiconductor die having a first major surface;
a schottky barrier structure connected to a portion of said first major surface;
a first electrode electrically connected to said schottky barrier structure;
a second electrode electrically connected to said first major surface of said semiconductor die, but spaced from said first electrode;
a plurality of solder bumps at least one of which is connected to one said first electrode and said second electrode; and
a guard ring formed in said semiconductor die in a region at least partly between said first electrode and said second electrode, wherein said second electrode surrounds said first electrode, and wherein said semiconductor die includes a first lightly doped portion and a second highly doped portion, said first lightly doped portion being disposed over said second highly doped portion, and further comprising a sinker extending from a major surface of said first lightly doped portion to said second lightly doped portion, wherein said second electrode is electrically connected to said sinker.
5. A semiconductor device package according to claim 4 , wherein said guard ring is around the periphery of said first electrode.
6. A semiconductor device package according to claim 1 , wherein said schottky structure is a layer of molybdenum.
7. A semiconductor device package according to claim 1 , wherein said first electrode is an anode electrode and said second electrode is a cathode electrode.
8. A semiconductor device package according to claim 1 , wherein said semiconductor die includes a first lightly doped portion and a second highly doped portion, said first lightly doped portion being disposed over said second highly doped portion, and further comprising a sinker extending from a major surface of said first portion to said second portion, wherein said second electrode is electrically connected to said sinker.
9. A semiconductor device package according to claim 8 , wherein said sinker comprises a highly doped region in said first lightly doped portion.
10. A semiconductor device package according to claim 1 , further comprising a layer of nickel disposed between at least one of said plurality of solder bumps and its associated electrode.
11. A semiconductor device package according to claim 1 , wherein said schottky structure comprises a layer of palladium.
12. A semiconductor device package according to claim 1 , wherein said schottky structure comprises a layer of vanadium.
13. A semiconductor device package according to claim 1 , wherein said first electrode comprises of aluminum.
14. A semiconductor device package according to claim 1 , wherein said second electrode comprises aluminum.
15. A semiconductor device package according to claim 2 , wherein said passivation layer comprises of silicon nitride.
16. A semiconductor device package according to claim 1 , wherein said semiconductor die includes a second major surface opposite to said first major surface, said second major surface being free of any electrical connection.
17. A semiconductor device package according to claim 1 , wherein said semiconductor die includes side edges which define lateral boundaries for said semiconductor device package.
18. A semiconductor device package according to claim 4 , further comprising a passivation layer disposed over said first electrode and said second electrode, wherein said plurality of solder bumps are disposed over a free surface of said passivation layer and extend through openings in said passivation layer to said first and second electrodes.
19. A semiconductor device package according to claim 4 , wherein said schottky structure is a layer of molybdenum.
20. A semiconductor device package according to claim 4 , wherein said first electrode is an anode electrode and said second electrode is a cathode electrode.
21. A semiconductor device package according to claim 4 , wherein said semiconductor die includes a first lightly doped portion and a second highly doped portion, said first lightly doped portion being disposed over said second highly doped portion, and further comprising a sinker extending from a major surface of said first portion to said second portion, wherein said second electrode is electrically connected to said sinker.
22. A semiconductor device package according to claim 21 , wherein said sinker comprises a highly doped region in said first lightly doped portion.
23. A semiconductor device package according to claim 4 , further comprising a layer of nickel disposed between at least one of said plurality of solder bumps and its associated electrode.
24. A semiconductor device package according to claim 4 , wherein said schottky structure comprises a layer of palladium.
25. A semiconductor device package according to claim 4 , wherein said schottky structure comprises a layer of vanadium.
26. A semiconductor device package according to claim 4 , wherein said first electrode comprises of aluminum.
27. A semiconductor device package according to claim 4 , wherein said second electrode comprises aluminum.
28. A semiconductor device package according to claim 18 , wherein said passivation layer comprises of silicon nitride.
29. A semiconductor device package according to claim 4 , wherein said semiconductor die includes a second major surface opposite to said first major surface, said second major surface being free of any electrical connection.