Data signal processing method and data processor implementing independent and asynchronous system and data clocks

1. A method of digital signal data transmission and data processing in a system having a plurality of data processors connected in a sequence by a communication medium, comprising the steps of:

providing a synchronization signal for the system;

generating data clock signals from the synchronization signal for use in data transmission through the medium from one data processor to the next in the sequence;

generating respective system clock signals for use in data processing within each of the plurality of data processors,

the data clock signals and the system clock signals being independent of each other in clock rate;

creating data processing enable signals from said data clock signals and said respective system clock signals within each processor;

transferring data from one data processor to a subsequent data processor in the sequence under control of said data clock signals; and

performing data processing on received data at predetermined cycles of the system clock signals.

2. The digital signal processing method as set forth in claim 1 , wherein said system clock is fixed at a clock rate much higher than said data clock.

3. The digital signal processing method as set forth in claim 1 , wherein

said data processing enable signal is created by regarding a first cycle of said system clock satisfying a specific electric characteristic in a cycle of said data clock, as an enable signal, and

the processing is suspended until the next enable signal after data processing of the data at the predetermined cycle number of said system clock.

4. A data processor comprising:

a data intake unit for receiving data transmitted from another data processor connected thereto by a communication medium;

a data clock generating unit responsive to an incoming synchronization clock to generate a data clock,

wherein the synchronization clock is used by a plurality of data processors which receive and transmit data from one to another in a sequence through the communication medium;

a system clock generating unit for creating a system clock independent of the data clock, for use in data processing within the processor;

a data processing unit which receives data from said data intake unit and performs data processing on the received data at predetermined cycles of said system clock; and

an enable signal creating unit responsive to said data clock and said system clock which creates an enable signal for enabling and disabling data processing in said data processing unit,

wherein said intake unit is operative to take in received data, according to the state of the enable signal.

5. The data processor as set forth in claim 4 , wherein said data processing unit performs the data processing at the predetermined cycle number of said system clock and thereafter suspends processing until the next enable signal.

6. The data processor as set forth in claim 4 , wherein said system clock is fixed at a clock rate much higher than said data clock.

7. The data processor as set forth in claim 4 , further comprising a data processing controlling unit operating by said system clock for controlling or performing the data processing through communication with said data processing unit.

8. The data processor as set forth in claim 4 , further comprising a data holding unit which receives and holds data processed in said data processing unit and supplies the data to a posterior processor in synchronization with said data clock.

9. The data processor as set forth in claim 4 , wherein the synchronization clock is derived from the transmitted data.

10. The data processor as set forth in claim 9 , wherein said data processing unit performs the data processing at the predetermined cycle number of said system clock and thereafter suspends processing until the next enable signal.

11. The data processor as set forth in claim 9 , wherein said system clock is fixed at a clock rate much higher than said data clock.

12. The data processor as set forth in claim 9 , further comprising a data processing controlling unit operating by the system clock for controlling or performing the data processing through communication with said data processing means.

13. The data processor as set forth in claim 9 , further comprising a data holding unit for receiving and holding the data processed in said data processing means and supplying the data to a posterior processor in synchronization with said data clock.

14. The data processor as set forth in claim 4 , wherein the synchronization clock is supplied separately from the transmitted data.

15. The data processor as set forth in claim 14 , wherein said data processing unit performs the data processing at the predetermined cycle number of said system clock and thereafter suspends processing until the next enable signal.

16. The data processor as set forth in claim 14 , wherein said system clock is fixed at a clock rate much higher than said data clock.

17. The data processor as set forth in claim 14 , further comprising:

a data processing controlling unit operating by said system clock for controlling or performing the data processing through communication with said data processing unit.

18. The data processor as set forth in claim 14 , further comprising a data holding unit which receives and holds data processed in said data processing unit and supplies the data to a posterior processor in synchronization with said data clock.

19. A data processor as set forth in claim 4 , wherein said data processing unit is operative to receive data according to the state of the enable signal.