IP Library Granted Patent US 6,744,690
Granted Patent Utility
US 6,744,690 · Confirmation No. 9738

ASYNCHRONOUS INPUT DATA PATH TECHNIQUE FOR INCREASING SPEED AND REDUCING LATENCY IN INTEGRATED CIRCUIT DEVICES INCORPORATING DYNAMIC RANDOM ACCESS MEMORY (DRAM) ARRAYS AND EMBEDDED DRAM

Inventor: Michael C. Parris
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Code Description Pages PDF
2020-06-11 OATH Oath or Declaration filed 262 View
2010-11-04 R3.73 Assignee showing of ownership per 37 CFR 3.73 1 View
2010-11-04 PA.. Power of Attorney 1 View
2010-11-04 N417 Electronic Filing System Acknowledgment Receipt 2 View
2004-03-16 IFEE Issue Fee Payment (PTO-85B) 1 View
2003-12-22 NOA Notice of Allowance and Fees Due (PTOL-85) 3 View
2003-12-22 NOA Notice of Allowance and Fees Due (PTOL-85) 3 View
2003-12-22 892 List of references cited by examiner 1 View
2003-12-22 IIFW Issue Information including classification, examiner, name, claim, renumbering, etc. 1 View
2003-12-22 FWCLM Index of Claims 1 View
2003-12-22 SRFW Search information including classification, databases and other search related notes 1 View
2003-12-10 SRNT Examiner's search strategy and results 2 View
2002-11-07 TRNA Transmittal of New Application 3 View
2002-11-07 SPEC Specification 14 View
2002-11-07 CLM Claims 4 View
2002-11-07 ABST Abstract 1 View
2002-11-07 DRW Drawings-only black and white line drawings 5 View
2002-11-07 OATH Oath or Declaration filed 2 View
2002-11-07 TRNA Transmittal of New Application 3 View
2002-11-07 SPEC Specification 14 View
2002-11-07 CLM Claims 4 View
2002-11-07 ABST Abstract 1 View
2002-11-07 DRW Drawings-only black and white line drawings 5 View
2002-11-07 OATH Oath or Declaration filed 2 View
2002-11-07 WFEE Fee Worksheet (SB06) 1 View
2002-11-07 WFEE Fee Worksheet (SB06) 1 View
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Quick Facts
Patent No.
US 6,744,690
App. No.
10/289,736
Filed
2002-11-07
Granted
2004-06-01
Pub. No.
US20040090855A1
Examiner
LAM, DAVID
Art Unit
2818
PTA
0 days