Mapping addresses to memory banks based on at least one mathematical relationship
View Patent ↗One embodiment of the invention is a memory controller that maps a received address to a memory location in a plurality of memory banks, the memory controller comprising: circuitry for calculating a remainder from a division of the received address by a divisor, wherein the divisor is based on the number of the plurality of banks; circuitry for determining a particular bank of the plurality of banks based on the remainder and at least one bit of the received address; and circuitry for determining the memory location in the particular bank using at least a portion of the received address.
1. A memory controller that maps a received address to a memory location in a plurality of memory banks, the memory controller comprising:
circuitry for calculating a remainder from a division of the received address by a divisor, wherein the divisor is based on the number of the plurality of banks;
circuitry for determining a particular bank of the plurality of banks based on the remainder and at least one bit of the received address; and
circuitry for determining the memory location in the particular bank using at least a portion of the received address.
2. The memory controller of claim 1 , wherein the divisor is equal to the number of the plurality of banks minus one.
3. The memory controller of claim 1 , wherein the divisor is a prime number.
4. The memory controller of claim 1 , wherein the number of memory banks is equal to 2 N and the at least one bit of the received address is equal to N bits.
5. The memory controller of claim 4 , wherein 2 N −1 is a non-prime number, wherein the memory controller further comprises:
circuitry for grouping the plurality of memory banks into 2 M groups wherein 2 M −1 is a prime number.
6. The memory controller of claim 5 , wherein the divisor is 2 M −1 and the at least one bit of the received address is equal to M+1 bits.
7. The memory controller of claim 1 , wherein the number of memory banks is equal to four, the divisor is equal to three, and the at least one bit is equal to 2 bits.
8. The memory controller of claim 1 , wherein the portion of the received address is exclusive of the at least one bit of the received address.
9. The memory controller of claim 1 , wherein the received address is a physical address associated with a memory access request.
10. The memory controller of claim 1 , further comprising:
a reorder buffer;
wherein the reorder buffer holds at least one memory access request that is associated with the received address and conflicts with another memory access request that maps to the particular bank.
11. The memory controller of claim 1 , further comprising:
logic for accessing the memory location to allow processing of a memory access request associated with the received address.
12. The memory controller of claim 1 , wherein the plurality of memory banks are a portion of a DRAM memory system.
13. The memory controller of claim 1 , wherein a maximum realizable bandwidth of the memory controller is greater than 0.75B, wherein B is a maximum usage of a data bus of the memory banks.
14. A method for mapping an address to a particular bank of a plurality of memory banks, the method comprising:
receiving the address;
dividing the address by a divisor, wherein the divisor is based on the number of the plurality of memory banks; and
determining the particular bank based on a remainder of the step of dividing and at least one bit of the address.
15. The method of claim 14 , further comprising:
determining a memory location in the particular bank using at least a portion of the address.
16. The method of claim 14 , wherein the divisor is equal to the number of the plurality of banks minus one.
17. The method of claim 14 , wherein the divisor is a prime number.
18. The method of claim 14 , wherein the number of memory banks is equal to 2 N and the at least one bit of the received address is equal to N bits.
19. The method of claim 18 , wherein 2 N −1 is a non-prime number, wherein the method further comprises:
grouping the plurality of memory banks into 2 M groups, wherein 2 M −1 is a prime number.
20. The method of claim 19 , wherein the divisor is 2 M −1 and the at least one bit of the address is equal to M+1 bits.
21. The method of claim 14 , wherein the portion of the address is exclusive of the at least one bit of the address.
22. The method of claim 14 , further comprising:
holding at least one memory access request that is associated with the address and conflicts with another memory access request that maps to the particular bank.
23. The method of claim 14 , further comprising:
accessing the memory location to allow processing of a memory access request associated with the received address.
24. A system for mapping an address to a particular bank of a plurality of memory banks comprising:
means for dividing the address by a divisor, wherein the divisor is based on the number of the plurality of memory banks and forming a remainder; and
means for determining the particular bank based on the remainder and at least one bit of the address.
25. A computer system comprising:
a plurality of memory banks;
a memory controller that receives a memory access request that includes an address and maps the address to a particular location in the plurality of memory banks based on at least one bit of the address and a remainder of the address divided by a number associated with the number of the plurality of memory banks; and
circuitry for accessing the particular location using at least a portion of the received address.