Liquid crystal display and driving method thereof

1. A method of driving a liquid crystal display having a plurality of liquid crystal cells arranged in a matrix type, said method comprising the steps of:

providing a gate driver for receiving a gate voltage from a pulse voltage generator, a gate start pulse and a gate output enable signal to generate at least one gate pulse having a desired falling slope;

applying video signals to a plurality of data lines connected to the liquid crystal cells; and

sequentially applying the at least one gate pulse having the desired falling slope to a plurality of gate lines connected to the liquid crystal cells in a direction crossing the data lines,

wherein the pulse voltage generator is directly connected to a first switching device of the gate driver, and

wherein the pulse voltage generator includes:

first and second resistors connected, in series, between an input terminal supplied with a gate shift clock signal and a ground voltage source, a first transistor commonly connected to the first and second resistors;

third and fourth resistors connected,in series, between the first transistor and a first voltage source;

a second transistor commonly connected to the third and fourth resistors;

a third transistor connected to the first transistor;

fifth and sixth resistors connected, in series, between the third transistor and the first voltage source;

an eighth resistor commonly connected to the fifth and sixth resistors;

a seventh resistor connected between a fourth transistor and the second transistor;

a ninth resistor provided between the second transistor and the ground voltage source; and

an output terminal connected to the ninth resistor.

2. The method as claimed in claim 1 , wherein said gate pulse includes the steps of:

rising from a first voltage into a second voltage;

remaining at said second voltage;

falling from said second voltage into a third voltage higher than said first voltage at a desired slope; and

falling from said third voltage into said first voltage.

3. The method as claimed in claim 1 , wherein first and second gate pulses of the at least one pulse having the desired falling slope are applied to the gate lines in such a manner to be spaced by one horizontal period.

4. The method as claimed in claim 3 , wherein the second gate pulse applied to the nth gate line (wherein n is an integer) and the first gate pulse applied to the (n+2)th gate line are applied substantially at the same time.

5. A method of driving a liquid crystal display having a plurality of liquid crystal cells arranged in a matrix type, said method comprising the steps of:

applying video signals to a plurality of data lines connected to the liquid crystal cells;

applying a first gate pulse having a desired falling slope to any one of a plurality of gate lines connected to the liquid crystal cells in a direction crossing the data lines; and

applying a second gate pulse having a rectangular waveform to the gate line supplied with the first gate pulse in such a manner to be spaced by one horizontal period from the first gate pulse.

6. The method as claimed in claim 5 , wherein the first gate pulse applied to the nth gate line (wherein n is an integer) and the second gate pulse applied to the (n+2)th gate line are applied at the same time.

7. The method as claimed in claim 5 , wherein said first gate pulse includes the steps of:

rising from a first voltage into a second voltage;

remaining at said second voltage;

falling from said second voltage into a third voltage higher than said first voltage at a desired slope; and

falling from said third voltage into said first voltage.

8. A liquid crystal display, comprising:

a pulse voltage generator for receiving a gate shift clock signal to generate at least one gate voltage having a desired falling slope; and

a gate driver for receiving said gate voltage, a gate start pulse and a gate output enable signal to generate at least one gate pulse having a desired falling slope,

wherein the pulse voltage generator is directly connected to a first switching device of the gate driver, and

wherein the pulse voltage generator includes:

first and second resistors connected, in series, between an input terminal supplied with a gate shift clock signal and a around voltage source, a first transistor commonly connected to the first and second resistors;

third and fourth resistors connected, in series, between the first transistor and a first voltage source;

a second transistor commonly connected to the third and fourth resistors;

a third transistor connected to the first transistor;

fifth and sixth resistors connected, in series, between the third transistor and the first voltage source;

an eighth resistor commonly connected to the fifth and sixth resistors;

a seventh resistor connected between a fourth transistor and the second transistor;

a ninth resistor provided between the second transistor and the ground voltage source; and

an output terminal connected to the ninth resistor.

9. The liquid crystal display as claimed in claim 8 , said gate driver includes:

an AND gate supplied with said gate start pulse;

an inverter for receiving said gate output enable signal and inverting the received gate output enable signal to apply it to the AND gate; and

a second switching device turned on by a second control signal from the AND gate,

wherein the first switching device is turned on by a first control signal from the AND gate.

10. The liquid crystal display as claimed in claim 9 , wherein said AND gate generates said first control signal when said inverted gate output enable signal and said gate start pulse have a high logic while generating said second control signal at the remaining time.

11. The liquid crystal display as claimed in claim 9 , wherein said first switching device receives said gate voltage while said second switching device receives a voltage lower than said gate voltage.

12. A liquid crystal display, comprising:

a pulse voltage generator for receiving a gate shift clock signal to generate at least one gate voltage having a desired falling slope; and

a gate driver for receiving said gate voltage, a gate start pulse and a gate output enable signal to generate a first gate pulse having a rectangular waveform and a second gate pulse having a desired slope.

13. The liquid crystal display as claimed in claim 12 , wherein said gate driver includes:

an AND gate supplied with said gate start pulse;

an inverter for receiving said gate output enable signal and inverting the received gate output enable signal to apply it to the AND gate;

a first switching device turned on by a first control signal from the AND gate; and

a second switching device turned on by a second control signal from the AND gate.

14. The liquid crystal display as claimed in claim 13 , wherein said AND gate generates said first control signal when said inverted gate output enable signal and said gate start pulse have a high logic while generating said second control signal at the remaining time.

15. The liquid crystal display as claimed in claim 13 , wherein said first switching device receives said gate voltage while said second switching device receives a voltage lower than said gate voltage.

16. The liquid crystal display as claimed in claim 12 , further comprising:

a modified shift clock generator for receiving said gate shift clock signal and generating a modified gate shift clock signal remaining at a high state during two and one half period of said gate shift clock signal while remaining at a low state during a half period of said gate clock signal to apply it to the pulse voltage generator.