Receiving circuit for receiving messages signals

1. A receiving circuit for receiving message signals, having a first sampler for converting the message signal into a first sampled signal by a first sampling method, having at least one second sampler connected in parallel to the first sampler for converting the message signal into a second sampled signal by a second sampling method, and having an analyzing unit for decoding the first sampled signal and/or the second sampled signal and checking them for errors.

2. A receiving circuit as claimed in claim 1 , characterized in that the first sampler has a first decoder connected downstream of it, and the second sampler has a second decoder connected downstream of it, and in that the analyzing unit selects the output signal from the first decoder or the second decoder for further message processing as a function of error messages from the first and second decoders.

3. A receiving circuit as claimed in claim 1 , characterized in that the analyzing unit has a control unit, a switch, and a checking unit, in that error messages from the first and second decoders are fed to the control unit, in that the output signal from the first or second decoder can be fed to the checking unit by means of the switch, and in that the control unit operates the switch as a function of the error messages from the first and second decoders.

4. A receiving circuit as claimed in claim 1 , characterized in that a memory is provided by means of which the sampled signal from either the first or the second sampler can be buffer-stored, in that the analyzing unit is designed for analyzing the sampled signal from one sampler in a first step and, if one or more errors is detected, to analyze the sampled signal from the other sampler, which was buffer-stored in the memory, in a second step.

5. A receiving circuit as claimed in claim 4 , characterized in that the analyzing unit has a control unit, a decoder, and a checking unit, in that error messages from the decoder and the checking unit are fed to the control unit, in that switching means are associated with the control unit, by which switching means the sampled signal from either the first or the second sampler can be fed directly to the decoder, or alternatively the sampled signal from the respective other sampler, which was buffer-stored in the memory, can be fed to the decoder.

6. A receiving circuit as claimed in claim 1 , characterized in that provision is made in the first sampler for sampling in a fixed sampling pattern as a first sampling method, and provision is made in the second sampler for sampling with bitwise resynchronization as a second sampling method.

7. A receiving circuit as claimed in claim 1 , characterized in that the coded message signal is an edge-coded signal.

8. A receiving circuit as claimed in claim 1 , characterized in that the sampler is implemented in the form of an analog-to-digital converter.

9. A receiving circuit as claimed in claim 1 , characterized in that the sampler is implemented in the form of a threshold discriminator.

10. A method of receiving coded message signals, wherein the message signal is converted into a first sampled signal by means of a first sampling method, wherein the message signal is converted into a second sampled signal by means of a second sampling method in parallel with the first sampling method, and wherein the first sampled signal and/or the second sampled signal are analyzed as desired.