Granted Patent B2

US 7,116,677 · App. 10/294,995 · Granted Oct 3, 2006

Abstract

Claims (58)

1. An apparatus comprising:

a circuit that is configured to:

receive and transmit data blocks;

receive a selection data block (SDB);

produce and transmit an identification data block (IDB); and

time slot fix an n th time slot of a plurality of time slot sequences; and

a controller that is configured to enable communication from the circuit during the nth time slot.

2. The apparatus of claim 1 , wherein:

the IDB is transmitted during a duration of the n th time slot of the plurality of time slot sequences (TSS).

3. The apparatus of claim 1 , wherein

the controller includes a comparator and a sequencer.

4. The apparatus of claim 3 , wherein

the comparator is configured to enable the communication based on a comparison of a time slot register and a time slot counter.

5. The apparatus of claim 1 , wherein

the circuit is configured to:

receive an acknowledge data block (QDB)

set the circuit to a selected state based on receipt of the QDB.

6. The apparatus of claim 1 , wherein

the controller is configured to enable conununication from the circuit only during the n th time slot.

7. The apparatus of claim 1 , wherein

the circuit is configured to determine each time slot of the plurality of time slot sequences.

8. The apparatus of claim 5 , wberein

the circuit is configured to receive the QDB in response to the transmission of the IDB.

9. An apparatus comprising:

a circuit that is configured to:

receive data blocks;

receive a selection data block (SDB); and

time slot fix an n th time slot of a plurality of time slot sequences; and

controller that is configured to enable communication from the circuit only during the nth time slot of the plurality of time slot sequences.

10. A receiving and transmission device comprising:

a means for receiving a selection data block (SDB);

a means for producing an identification data block (IDB) and transmitting the IDB;

a means for fixing an n th time slot of a plurality of time slot sequences; and

a means for enabling communication during the nth time slot of the plurality of time slot sequences.

11. The receiving and transmission device of claim 10 , wherein

the means for enabling communication enables communication only during the n th time slot of the plurality of time slot sequences.

12. A method comprising:

receiving a selection data block (SDB);

transmitting an identification data block (IDB) in response to receipt of the SDB;

fixing an n th time slot of a plurality of time slot sequences; and

enabling communication from the circuit during the nth time slot.

13. The method of claim 12 , further comprising:

comparing an output of a time slot register with an output of a time slot counter to enable the communication from the circuit.

14. The method of claim 12 , further comprising:

enabling communication from the circuit only during the n th time slot.

15. The method of claim 12 , further comprising:

receiving an acknowledge data block (QDB), and

setting the circuit to a selected state upon receipt of the QDB.

16. A method comprising:

receiving a selection data block at a data carrier;

recognizing the data carrier as being selected from amongst a plurality of data carriers;

outputting from the data carrier an identification data block during a duration of an n th time slot of a time sequence; and

controlling subsequent communication from the data carrier to occur only during the n th time slot.

17. A method comprising:

receiving a selection data block at a data carrier;

in response to receiving the selection data block, recognizing the data carrier as being selected from amongst a plurality of data carriers;

in response to the recognizing, outputting from the data carrier an identification data block during a duration of an nth time slot of a time sequence; and

controlling communication from the data carrier to occur only during the nth time slot.

Assignments (8)