Edge synchronized phase-locked loop circuit
View Patent ↗A phase-locked loop circuit for synchronizing an edge of an output signal with an edge of an input signal. The circuit detects an edge of an input clock signal, and a corresponding edge on an output signal. If the output signal edge is out of phase with the input clock edge, the circuit shifts the output signal by 180 degrees to effectively produce a single double-length clock phase. The synchronized phase-locked loop circuit provides predictable phase-locked loop output phase synchronization with an input clock.
1. A phase-locked loop circuit for synchronizing an output clock signal with an input clock signal, said circuit comprising:
a first edge detector for detecting an input edge of the input clock signal;
a second edge detector for detecting a corresponding edge of the output clock signal, said corresponding edge being produced by and simultaneous with the input edge; and
a phase shift controller for shifting the output clock signal by 180 degrees to produce a single double-length clock phase.
2. The phase-locked loop circuit according to claim 1 , wherein the phase shift controller is applied only if the corresponding edge is out of phase with the input edge.
3. The phase-locked loop circuit according to claim 2 , wherein the phase shift controller synchronizes the output clock signal with the input clock signal, so that a rising edge of the input clock signal produces a rising edge in the output clock signal.
4. The phase-locked loop circuit according to claim 2 , further comprising:
a voltage controlled oscillator for generating said output clock signal in response to an input voltage;
a phase detector for comparing said input signal to a feedback signal from said voltage controlled oscillator and generating an error signal; and
a loop filter for generating said input voltage in response to said error signal.
5. The phase-locked loop circuit according to claim 4 , further comprising a frequency divider for dividing said output clock signal from said voltage controlled oscillator to produce said feedback signal.
6. The phase-locked loop circuit according to claim 1 , wherein the phase shift controller comprises an exclusive OR gate through which the output clock signal is inverted.
7. The phase-locked loop circuit according to claim 4 , wherein:
a change in the ratio between the frequency of the input clock signal and frequency of the output clock signal re-establishes synchronization of the output signal with the input signal after at most one incorrect clock edge.
8. A method of synchronizing an output clock signal to an input clock signal in a phase-locked loop circuit, said method comprising:
detecting an edge of the input clock signal;
detecting a corresponding edge of the output clock signal, said corresponding edge being produced by and occurring simultaneously with the edge of the input clock signal;
comparing the corresponding edge to the edge of the input clock signal;
determining whether the output clock signal is in phase with the input clock signal; and
shifting the output clock signal by 180 degrees if the output clock signal is determined to be out of phase with the input clock signal.
9. A method according to claim 8 , wherein the edge of the input clock signal is a rising edge.
10. A method according to claim 8 , wherein the edge of the input clock signal is a falling edge.
11. A method according to claim 8 , wherein the step of shifting the output clock signal by 180 degrees effectively creates a single double-length clock phase in order to synchronize the output clock signal with the input clock signal.
12. A method according to claim 8 , wherein the output clock signal is inverted through an exclusive OR gate in order to shift the signal by 180 degrees.
13. A phase-locked loop circuit for synchronizing an output clock signal with an input clock signal, said circuit comprising:
a voltage controlled oscillator for generating said output clock signal in response to an input voltage and providing a feedback signal;
a phase detector for comparing said input signal to the feedback signal and generating an error signal;
a loop filter for generating said input voltage in response to said error signal;
a first edge detector for detecting a rising edge of the input clock signal;
a second edge detector for detecting a corresponding edge of the output clock signal, said corresponding edge being produced by and simultaneous with the rising edge; and
a phase shift controller for shifting the output clock signal to synchronize a phase of the output clock signal with a phase of the input clock signal.
14. The phase-locked loop circuit of claim 13 , wherein said phase-shift controller shifts the output clock signal only if the corresponding edge is falling.
15. The phase-locked loop circuit of claim 13 , wherein the phase-shift controller shifts the output clock signal by 180 degrees.
16. The phase-locked loop circuit of claim 13 , wherein said phase-shift controller comprises an exclusive OR logic gate.
17. The phase-locked loop circuit of claim 16 , wherein said output clock signal is passed through the exclusive OR logic gate.
18. The phase-locked loop circuit of claim 17 , wherein said exclusive OR logic gate inverts the output clock signal to synchronize the phase of the output clock signal with the phase of the input clock signal.
19. The phase-locked loop circuit of claim 18 , wherein said exclusive OR logic gate inverts the output clock signal if the corresponding edge is falling.
20. The phase-locked loop circuit of claim 13 , further comprising a frequency divider for dividing said output clock signal from said voltage controlled oscillator to produce said feedback signal.