Clock and data recovery with extended integration cycles
View Patent ↗Clock and data recovery circuitry includes an interleaved sampler having multiple integrators, where at least one of the integrators integrates the input data for at least two unit intervals (UIs). One embodiment includes a four-way interleaved sampler, where each integrator in the sampler integrates the input data for two UIs, where each integrator is sampled at or near the middle of its two-UI integration cycle. In an exemplary 10-GHz system, the reset cycle of each integrator may begin many tens of picoseconds after the data is sampled. Since the signal is sampled near the center of the integration cycle and is not highly proximate to the time of the integrator reset, the latch signal has a window of uncertainty extending into the length of a data bit cell with little possibility of latching erroneous data. The sensitivity of the clock recovery circuitry may be optimized by centering the latch function over the time of highest signal level, thereby maximizing signal-to-noise ratio.
1. A method for recovering data from an input data stream, the method comprising the steps of:
(a) integrating the input data stream using multiple independent integrators that are operating out-of-phase relative to one another, wherein at least one integrator has an integration period of more than one unit interval (UI) and at least one integrator has a non-integration period of more than one UI;
(b) processing the output of each integrator to recover the data from the input data stream;
(c) sampling the input data stream substantially during of one or more transitions using one or more edge samplers; and
(d) generating one or more clocks based on the output of each edge sampler and the recovered data, wherein the one or more clocks are used to determine when to sample the output of each integrator and when to sample the input data stream by each edge sampler, wherein:
step (a) comprises the step of integrating the input data stream using four independent integrators, each of which integrates the input data stream for substantially two UI and which are staggered in time by one-UI increments; and
step (b) comprises the step of sampling each integrator substantially at the center of its integration period.
2. A method for recovering data from an input data stream, the method comprising the steps of:
(a) integrating the input data stream using multiple independent integrators that are operating out-of-phase relative to one another, wherein at least one integrator has an integration period of more than one unit interval (UI) and at least one integrator has a non-integration period of more than one UI;
(b) processing the output of each integrator to recover the data from the input data stream;
(c) sampling the input data stream using two edge samplers; and
(d) generating four sampling clocks based on the outputs of the two edge samplers and the recovered data, wherein the four sampling clocks are staggered in time by one-UI increments, wherein:
step (a) comprises the step of integrating the input data stream using four independent integrators, each of which integrates the input data stream for substantially two UI and which are staggered in time by one-UI increments;
step (b) comprises the step of sampling each integrator substantially at the center of its integration period.
3. An apparatus for recovering data from an input data stream, the apparatus comprising:
(a) multiple independent integrators configured to integrate the input data stream, wherein the integrators operate out-of-phase relative to one another, wherein at least one integrator has an integration period of more than one unit interval (UI) and at least one integrator has a non-integration period of more than one UI; and
(b) circuitry configured to process the output of each integrator to recover the data from the input data stream, wherein:
the apparatus comprises four independent integrators staggered in time by one-UI increments, wherein each integrator integrates the input data stream for substantially two UI;
the circuitry is configured to sample each integrator substantially at the center of its integration period;
the apparatus further comprises one or more edge samplers configured to sample the input data stream substantially during one or more transitions; and
the circuitry is configured to generate one or more clocks based on the output of each edge sampler and the recovered data, wherein the one or more clocks are used to determine when to sample the output of each integrators and when to sample the input data stream by each edge sampler.
4. An apparatus for recovering data from an input data stream, the apparatus comprising:
(a) multiple independent integrators configured to integrate the input data stream, wherein the integrators operate out-of-phase relative to one another, wherein at least one integrator has an integration period of more than one unit interval (UI) and at least one integrator has a non-integration period of more than one UI; and
(b) circuitry configured to process the output of each integrator to recover the data from the input data stream, wherein:
the apparatus comprises:
four independent integrators staggered in time by one-UI increments, wherein each integrator integrates the input data stream for substantially two UI; and
two edge samplers; and
the circuitry is configured to:
sample each integrator substantially at the center of its integration period; and
generate four sampling clocks based on the outputs of the two edge samplers and the recovered data, wherein the four sampling clocks are staggered in time by one-UI increments.
5. The invention of claim 1 , wherein at least one integrator has intervals of integration interleaved with intervals of non-integration, wherein each interval of integration has a period of more than 1 UI.
6. The invention of claim 5 , wherein the at least one integrator is reset during each interval of non-integration.
7. The invention of claim 5 , wherein the intervals of integration and the intervals of non-integration are substantially the same length.
8. The invention of claim 1 wherein each integrator:
(1) has intervals of integration interleaved with intervals of non-integration, wherein each interval of integration and each interval of non-integration is substantially the same length, and more than 1 UI;
(2) is sampled substantially at the center of each of its intervals of integration; and
(3) is reset during each interval of non-integration.
9. The invention of claim 1 further comprising the step of recovering a clock signal from the input data stream.
10. The invention of claim 3 , wherein at least one integrator has intervals of integration interleaved with intervals of non-integration, wherein each interval of integration has a period of more than 1 UI.
11. The invention of claim 10 , wherein the at least one integrator is reset during each interval of non-integration.
12. The invention of claim 10 , wherein the intervals of integration and the intervals of non-integration are substantially the same length.
13. The invention of claim 3 , wherein each integrator:
(1) has intervals of integration interleaved with intervals of non-integration, wherein each interval of integration and each interval of non-integration is substantially the same length, and more than 1 UI;
(2) is sampled substantially at the center of each of its intervals of integration; and
(3) is reset during each interval of non-integration.
14. The invention of claim 3 , further comprising circuitry configured to recover a clock signal from the input data stream.
15. The invention of claim 5 , wherein each interval of non-integration has a period of more than one UI.
16. The invention of claim 10 , wherein each interval of non-integration has a period of more than one UI.
17. A method for recovering data from an input data stream, the method comprising the steps of:
(a) integrating the input data stream using multiple independent integrators that are operating out-of-phase relative to one another, wherein at least one integrator has an integration period of more than one unit interval (UI);
(b) processing the output of each integrator to recover the data from the input data stream;
(c) sampling the input data stream substantially during one or more transitions using one or more edge samplers; and
(d) generating one or more clocks based on the output of each edge sampler and the recovered data, wherein the one or more clocks are used to determine when to sample the output of each integrator and when to sample the input data stream by each edge sampler; wherein:
step (a) comprises the step of integrating the input data stream using four independent integrators, each of which integrates the input data stream for substantially two UI and which are staggered in time by one-UI increments;
step (b) comprises the step of sampling each integrator substantially at the center of its integration period;
step (c) comprises the step of sampling the input data stream using two edge samplers; and
step (d) comprises the step of generating four sampling clocks based on the outputs of the two edge samplers and the recovered data, wherein the four sampling clocks are staggered in time by one-UI increments.
18. An apparatus for recovering data from an input data stream, the apparatus comprising:
(a) multiple independent integrators configured to integrate the input data stream, wherein the integrators operate out-of-phase relative to one another, wherein at least one integrator has an integration period of more than one unit interval (UI);
(b) circuitry configured to process the output of each integrator to recover the data from the input data stream;
(c) one or more edge samplers configured to sample the input data stream substantially during one or more transitions; and
(d) the circuitry is configured to generate one or more clocks based on the output of each edge sampler and the recovered data, wherein the one or more clocks are used to determine when to sample the output of each integrator and when to sample the input data stream by each edge sampler; wherein:
the apparatus comprises:
four independent integrators staggered in time by one-UI increments, wherein each integrator integrates the input data stream for substantially two UI; and
two edge samplers; and
the circuitry is configured to:
sample each integrator substantially at the center of its integration period; and
generate four sampling clocks based on the outputs of the two edge samplers and the recovered data, wherein the four sampling clocks are staggered in time by one-UI increments.