Method and apparatus for configuring a programmable logic device
View Patent ↗A method and apparatus for configuring multiple first programmable logic devices from a single memory includes a microprocessor, and a second programmable logic device containing the interface logic for the first programmable device and the microprocessor. The present invention allows multiple FPGAs to be programmed from a single memory structure under the control of the microprocessor thereby using fewer components than systems dedicating a separate memory to each FPGA. A communications port allows new configurations to be downloaded to the microprocessor memory. In addition, the present invention can be used in combination with standard systems with each FPGA having its own memory, with the microprocessor being able to select between the central microprocessor memory and the local memory for programming each FPGA.
1. A method for configuring a plurality of programmable logic devices connected to a local data bus from a single memory device comprising the steps of:
communicating by a microprocessor connected to the local data bus through a communication port to which the microprocessor is directly connected;
signaling a reset line on all of the programmable logic devices;
selecting one of the programmable logic devices;
toggling a program reset line on the selected programmable logic device;
transmitting an initialization signal from the selected programmable logic device to the microprocessor;
determining the status of the selected programmable logic device from the initialization signal;
downloading a configuration from the single memory device connected to the microprocessor to the selected programmable logic device if there is no fault; and
selecting a second one of the programmable logic devices and performing the steps of toggling, transmitting, determining, and downloading on the second selected programmable logic device.
2. The method as in claim 1 , further comprising the step of transmitting a completion status signal from the selected programmable device to the microprocessor after the step of downloading is completed.
3. The method as in claim 2 , wherein the completion status signal indicates a successful download of the configuration.
4. The method as in claim 2 , wherein the completion status signal indicates a fault condition.
5. The method as in claim 4 , further comprising re-downloading a configuration from the single memory device to the selected programmable logic device.
6. The method as in claim 4 , further comprising the step of transmitting an alarm status to a user interface.
7. The method as in claim 6 , wherein the user interface is an alphanumeric display.
8. The method as in claim 6 , wherein the user interface is a light emitting diode.
9. The method as in claim 6 , wherein the user interface is a serial port.
10. The method of claim 6 , wherein the step of transmitting an alarm status to a user interface is performed by communicating by the microprocessor through the communication port.
11. The method as in claim 1 , further comprising the step of activating the programmable logic device.
12. The method as in claim 11 , wherein the step of activating is accomplished by the step of de-asserting the logic reset line.
13. The method as in claim 1 , further comprising the step of using an additional logic device to control reset lines of the plurality of programmable logic devices, and further comprising the microprocessor setting a command in the additional logic device.
14. The method as in claim 13 , wherein the command is an instruction as to which programmable logic device is to be selected.
15. The method of claim 1 , further comprising:
activating a designated programmable logic device that is a Field Programmable Gate Array (FPGA);
sending a command sequence from the microprocessor to an interface register in the FPGA to functionally test the FPGA;
evaluating a status signal by the microprocessor from the FPGA device; and
upon detection of a failure, transmitting a report through the communication port.
16. The method of claim 1 , wherein the step of communicating by the microprocessor includes receiving the configuration through the communication port, and further comprising:
transferring the configuration from the microprocessor to the single memory device.
17. An apparatus for configuring a plurality of programmable logic devices connected to a local data bus from a single memory device comprising:
means for communicating by a microprocessor connected to the local data bus through a communication port to which the microprocessor is directly connected;
means for signaling a reset line on all of the programmable logic devices;
means for selecting one of the programmable logic devices;
means for toggling a program reset line on the selected programmable logic device;
means for transmitting an initialization signal from the selected programmable logic device to the microprocessor;
means for determining the status of the selected programmable logic device from the initialization signal;
means for downloading a configuration from the single memory device, which is connected to the microprocessor, to the selected programmable logic device if there is no fault; and
means for selecting a second one of the programmable logic devices and performing the steps of toggling, transmitting, determining, and downloading on the second selected programmable logic device.
18. The apparatus as in claim 17 , further comprising means for transmitting a completion status signal from the selected programmable device to the microprocessor after the step of downloading is completed.
19. The apparatus as in claim 18 , wherein the completion status signal indicates a successful download of the configuration.
20. The apparatus as in claim 18 , wherein the completion status signal indicates a fault condition.
21. The apparatus as in claim 20 , further comprising means for re-downloading a configuration from the single memory device to the selected programmable device.
22. The apparatus as in claim 20 , further comprising means for transmitting an alarm status to a user interface.
23. The apparatus as in claim 22 , wherein the user interface is an alphanumeric display.
24. The apparatus as in claim 22 , wherein the user interface is a light emitting diode.
25. The apparatus as in claim 22 , wherein the user interface is a serial port.
26. The apparatus as in claim 22 , wherein transmitting the alarm to the user interface is performed by communicating by the microprocessor through the communication port.
27. The apparatus as in claim 17 , further comprising means for activating the selected programmable logic device.
28. The apparatus as in claim 27 , wherein the means for activating de-asserts the logic reset line.
29. The apparatus as in claim 17 , further comprising means for using an additional logic device to control reset lines of the plurality of programmable logic devices, and further comprising means for setting a command in the additional logic device.
30. The apparatus as in claim 29 , wherein the command is an instruction as to which programmable logic device is to be selected.
31. The apparatus as in claim 17 , further comprising:
means for activating a designated programmable logic device that is a Field Programmable Gate Array (FPGA);
means for sending a command sequence from the microprocessor to an interface register in the FPGA to functionally test the FPGA;
means for evaluating a status signal by the microprocessor from the FPGA device; and
upon detection of a failure, means for transmitting a report through the communication port.
32. The apparatus as in claim 17 , further comprising:
means for receiving the configuration by the microprocessor through the communication port; and
means for sending the configuration from the microprocessor to the memory device.