Multi-rate on-chip OCN filter for a transceiver system
View Patent ↗An apparatus and method are disclosed to aid a transceiver chip, in a wide-band serial data communications system, in receiving data at multiple data rates. A multi-rate filter within the transceiver chip is implemented as at least one adjustable-rate filter stage and a limiting stage. The at least one adjustable-rate filter stage is used to generate a filtered serial data signal from a received serial data signal. The limiter stage generates a full-swing serial data signal from the filtered serial data signal. A bandwidth of the at least one adjustable-rate filter stage is adjustable in order to receive serial data signals at multiple data rates. The bandwidth of the multi-rate filter within the transceiver chip is selectable by the user of the wide-band communication system.
1. In a transceiver chip used in high-speed serial data communications, apparatus to aid said transceiver chip in receiving data at multiple data rates, said apparatus comprising:
at least one multi-rate filter stage within said transceiver chip to generate a filtered serial data signal from a received serial data signal; and
a limiter stage within said transceiver chip to generate a full-swing serial data signal from said filtered serial data signal, said at least one multi-rate rate filter stage comprises at least one passive R-C circuit within said transceiver chip, wherein a capacitance value of said at least one passive R-C circuit is determined by a variable capacitor implemented within said transceiver chip as an N-MOS transistor in an N-well.
2. The apparatus of claim 1 wherein a bandwidth of said at least one multi-rate filter stage is adjustable in order to receive serial data signals at multiple data rates.
3. The apparatus of claim 1 wherein said at least one multi-rate filter stage comprises three first-order filter stages connected in series within said transceiver chip.
4. The apparatus of claim 1 wherein said at least one multi-rate filter stage comprises a low-pass filter within said transceiver chip.
5. The apparatus of claim 1 wherein said at least one multi-rate filter stage and said limiter stage eliminate ringing, of said received serial data signal, due to overshoot and undershoot of a predetermined signal threshold level by said serial data signal.
6. The apparatus of claim 1 wherein said N-MOS transistor comprises a varactor.
7. In a transceiver chip used in high-speed serial data communications, apparatus to aid said transceiver chip in receiving data at multiple data rates, said apparatus comprising:
at least one multi-rate filter stage within said transceiver chip to generate a filtered serial data signal from a received serial data signal; and
a limiter stage within said transceiver chip to generate a full-swing serial data signal from said filtered serial data signal, said at least one multi-rate rate filter stage comprises at least one passive R-C circuit within said transceiver chip, wherein a capacitance value of said at least one passive R-C circuit is determined by a variable capacitor implemented within said transceiver chip as parallel bank of capacitors and P-MOS and/or N-MOS transistors that are switched to ground and/or V DD .
8. The apparatus of claim 7 wherein a bandwidth of said at least one multi-rate filter stage is adjustable in order to receive serial data signals at multiple data rates.
9. The apparatus of claim 7 wherein said at least one multi-rate filter stage comprises three first-order filter stages connected in series within said transceiver chip.
10. The apparatus of claim 7 wherein said at least one multi-rate filter stage comprises a low-pass filter within said transceiver chip.
11. The apparatus of claim 7 wherein said at least one multi-rate filter stage and said limiter stage eliminate ringing, of said received serial data signal, due to overshoot and undershoot of a predetermined signal threshold level by said serial data signal.
12. In a transceiver chip used in high-speed serial data communications, apparatus to aid said transceiver chip in receiving data at multiple data rates, said apparatus comprising:
at least one multi-rate filter stage within said transceiver chip to generate a filtered serial data signal from a received serial data signal; and
a limiter stage within said transceiver chip to generate a full-swing serial data signal from said filtered serial data signal, said at least one multi-rate rate filter stage comprises at least one passive R-C circuit within said transceiver chip, wherein a resistance value of said at least one passive R-C circuit is determined by a variable resistor implemented within said transceiver chip as a parallel bank of resistors and P-MOS and/or N-MOS transistors that are switched to ground and/or V DD .
13. The apparatus of claim 12 wherein a bandwidth of said at least one multi-rate filter stage is adjustable in order to receive serial data signals at multiple data rates.
14. The apparatus of claim 12 wherein said at least one multi-rate filter stage comprises three first-order filter stages connected in series within said transceiver chip.
15. The apparatus of claim 12 wherein said at least one multi-rate filter stage comprises a low-pass filter within said transceiver chip.
16. The apparatus of claim 12 wherein said at least one multi-rate filter stage and said limiter stage eliminate ringing, of said received serial data signal, due to overshoot and undershoot of a predetermined signal threshold level by said serial data signal.
17. In a transceiver chip used in high-speed serial data communications, a method to aid said transceiver chip in receiving data at multiple data rates, said method comprising:
generating a filtered serial data signal from a received serial data signal by at least one multi-rate filter stage within said transceiver chip; and
generating a full-swing serial data signal from said filtered serial data signal by a limiter stage within said transceiver chip, said at least one multi-rate rate filter stage comprising at least one passive R-C circuit within said transceiver chip, wherein a capacitance value of said at least one passive R-C circuit is determined by a variable capacitor implemented within said transceiver chip as a parallel bank of capacitors and P-MOS and/or N-MOS transistors that are switched to ground and/or V DD .
18. The method of claim 17 wherein a bandwidth of said at least one multi-rate filter stage is adjustable in order to receive serial data signals at multiple data rates.
19. The method of claim 17 wherein said at least one multi-rate filter stage comprises three first-order filter stages connected in series within said transceiver chip.
20. The method of claim 17 wherein said at least one multi-rate filter stage comprises a low-pass filter within said transceiver chip.
21. The method of claim 17 wherein said at least one multi-rate filter stage and said limiter stage eliminate ringing, of said received serial data signal, due to overshoot and undershoot of a predetermined signal threshold level by said serial data signal.
22. In a transceiver chip used in high-speed serial data communications, a method to aid said transceiver chip in receiving data at multiple data rates, said method comprising:
generating a filtered serial data signal from a received serial data signal by at least one multi-rate filter stage within said transceiver chip; and
generating a full-swing serial data signal from said filtered serial data signal by a limiter stage within said transceiver chip, said at least one multi-rate rate filter stage comprising at least one passive R-C circuit within said transceiver chip, wherein a resistance value of said at least one passive R-C circuit is determined by a variable resistor implemented within said transceiver chip as a parallel bank of resistors and P-MOS and/or N-MOS transistors that are switched to ground and/or V DD .
23. The method of claim 22 wherein a bandwidth of said at least one multi-rate filter stage is adjustable in order to receive serial data signals at multiple data rates.
24. The method of claim 22 wherein said at least one multi-rate filter stage comprises three first-order filter stages connected in series within said transceiver chip.
25. The method of claim 22 wherein said at least one multi-rate filter stage comprises a low-pass filter within said transceiver chip.
26. The method of claim 22 wherein said at least one multi-rate filter stage and said limiter stage eliminate ringing, of said received serial data signal, due to overshoot and undershoot of a predetermined signal threshold level by said serial data signal.