Method of deforming a pattern and semiconductor device formed by utilizing deformed pattern
View Patent ↗A method of deforming a pattern comprising the steps of: forming, over a substrate, a layered-structure with an upper surface including at least one selected region and at least a re-flow stopper groove, wherein the re-flow stopper groove extends outside the selected region and separate from the selected region; selectively forming at least one pattern on the selected region; and causing a re-flow of the pattern, wherein a part of an outwardly re-flowed pattern is flowed into the re-flow stopper groove, and then an outward re-flow of the pattern is restricted by the re-flow stopper groove extending outside of the pattern, thereby to form a deformed pattern with at least an outside edge part defined by an outside edge of the re-flow stopper groove.
1. A semiconductor device comprising:
a gate electrode; and
a plurality of layers on said gate electrode,
wherein an entirety of a periphery of said gate electrode has a first height and an interior portion of said gate electrode has a second height less than said first height so that said gate electrode has a step, and
wherein an upper surface of at least a top one said plural layers has a step which is vertically aligned with said step of said gate electrode.
2. A semiconductor device comprising:
a substrate;
a gate electrode directly on said substrate; and
a plurality of layers on said gate electrode,
wherein an entirety of a first surface of said gate electrode directly contacts said substrate;
wherein an opposing second surface of said gate electrode has a peripheral portion surrounding an interior portion and having a first height and said interior portion having a second height less than said first height so that said gate electrode has a step, and
wherein an upper surface of at least a top one said plural layers has a step which is vertically aligned with said step of said gate electrode.
3. The semiconductor device as claimed in claim 2 , wherein said periphery portion is polygonal shaped.
4. The semiconductor device as claimed in claim 3 , wherein said polygonal shape is an octagon.
5. The semiconductor device as claimed in claim 2 , wherein an entirety of said first surface is in a single plane.
6. A semiconductor device comprising:
a gate electrode; and
a multi-layered structure on said gate electrode,
wherein said gate electrode has an inner portion and a peripheral portion surrounding said inner portion, said peripheral portion having a substantially uniform thickness,
wherein said inner portion has a reduced thickness so that said gate electrode has a step, and
wherein each layer of said multi-layered structure has a step which is positioned over said step of said gate electrode.