Integrated grating-outcoupled surface-emitting lasers
View Patent ↗An electronic/photonic integrated circuit in which grating-outcoupled surface-emitting lasers are used both to provide external emission out of the plane of the chip (through gratings), and also to feed optical power into photonic waveguides parallel to the plane of the chip. Transistors are fabricated in a common multilayer semiconductor body with the lasers.
1. A method for fabricating electronic/photonic integrated circuits, comprising the actions of:
(a) forming transistors and lateral-cavity lasers in a single body of monocrystalline semiconductor material; and
(b) forming gratings which outcouple light from at some ones of said lasers, to thereby form grating-outcoupled surface-emitting lasers;
(c) forming electrical connections to said transistors and said lasers; and
(d) forming lateral waveguide which provide optical interconnects to at least some ones of said lasers.
2. A method for fabricating electronic-photonic integrated circuits, comprising the actions of:
(a) forming transistors and lateral-cavity lasers in a single body of monocrystalline semiconductor material;
(b) forming gratings which outcouple light from at some ones of said lasers, to thereby form grating-outcoupled surface-emitting lasers; said lasers also comprising distributed reflectors having a difference period than said gratings; and
(c) forming electrical connections to said transistors and said lasers.
3. The method of claim 1 , wherein each said laser has a cavity which is defined solely by a distributed reflector.
4. The method of claim 1 , wherein said semiconductor material is epitaxially grown on a substrate which consists essentially of monocrystalline InP.
5. The method of claim 1 , wherein said body of said material comprises multiple substantially lattice-matched layers of III-V compound semiconductor material.
6. The method of claim 2 , wherein each said laser has a cavity which is defined solely by a distributed reflector.
7. The method of claim 2 , wherein said semiconductor material is epitaxially grown on a substrate which consists essentially of monocrystalline InP.
8. The method of claim 2 , wherein said body of said material comprises multiple substantially lattice-matched layers of III-V compound semiconductor material.