Calculating circuit for dividing a fixed-point signal

1. A calculating circuit for dividing a fixed-point input signal consisting of a sequence of n-bit-wide digital data values by an adjustable dividing factor 2 k for generating a divided fixed-point output signal, comprising:

(a) a signal input for applying the data value sequence of the fixed-point input signal;

(b) a first addition circuit which adds the digital data value present at the signal input to a data value temporarily stored in a register to form a first aggregate data value;

(c) a shift circuit which shifts the first aggregate data value present by k data bits to the right so that higher-order data bits of the first aggregate data value are delivered at an output of the shift circuit;

(d) a logic circuit which logically ANDs the k lower-order data bits of the first aggregate data value with a logical data value in the case of a logically low output control signal of a control logic and logically ORs these bits with an inverted logical data value in the case of a logically high output control signal of the control logic and delivers them to the register for temporarily storing the logically combined data value;

(e) a second addition circuit which adds the data value delivered by the shift circuit to one to form a second aggregate data value in the case of a logically high output control signal of the control logic;

(f) a signal output for delivering a sequence of the second aggregate data value as the divided fixed-point output signal;

(g) the control logic generating an output control signal which is logically high when the first aggregate data value is a negative number which cannot be divided by the dividing factor 2 k without remainder.

2. The calculating circuit as claimed in claim 1 , wherein the logical data value is equal to the dividing factor 2 k reduced by one.

3. The calculating circuit as claimed in claim 1 , wherein the logic circuit contains an inverter for inverting the logical data value.

4. The calculating circuit as claimed in claim 1 , wherein the logic circuit has an AND gate for logically ANDing the logical data value with the k lower-order data bits of the first aggregate data value.

5. The calculating circuit as claimed in claim 1 , wherein the logic circuit has an OR gate for logically ORing the inverted logical data value with the k lower-order data bits of the first aggregate data value.

6. The calculating circuit as claimed in claim 1 , wherein the second addition circuit has an adder for adding the data value delivered by the shift circuit to one to form the second aggregate data value, and has a multiplexer which switches the data value delivered by the shift circuit when a logically low output control signal is output by the control logic and the second aggregate data value generated by a second adder when a logically high output control signal is output by the control logic to the signal output of the calculating circuit.

7. The calculating circuit as claimed in claim 1 , wherein the dividing factor is a power value with the base two and an exponentiation factor k.

8. The calculating circuit as claimed in claim 1 , wherein the exponentiation factor k corresponds to the number of data bits which are shifted to the right by the shift circuit.

9. The calculating circuit as claimed in claim 1 , wherein the control logic has a sign detection circuit for detecting the sign of the first aggregate data value.

10. The calculating circuit as claimed in claim 9 , wherein the control logic has a first logical AND gate for logically ANDing the first aggregate data value with the logical data value.

11. The calculating circuit as claimed in claim 9 , wherein the sign detection circuit and a logical OR gate are connected to a second logical AND gate for generating the output control signal of the control logic.

12. The calculating circuit as claimed in claim 1 , wherein the logic circuit has an AND gate for logically ANDing the logical data value with the k lower-order data bits of the first aggragate data value and further wherein the logic circuit has an OR gate for logically ORing the inverted logical data value with the k lower-order data bits of the first aggragate data value.

13. The calculating circuit as claimed in claim 12 , wherein the logic circuit has a multiplexer comprising:

(a) a first input, which is connected to the output of the AND gate,

(b) a second input, which is connected to the output of the OR gate,

(c) an output, which is connected to the register, and comprising a control input, which is driven by the control logic.