Ferroelectric memory and operating method therefor
View Patent ↗A ferroelectric memory capable of improving disturbance resistance in a non-selected cell by increasing the ratio between voltages applied to ferroelectric capacitors of a selected cell and the non-selected cell respectively is obtained. This ferroelectric memory comprises a bit line, a word line arranged to intersect with the bit line and a memory cell including a switching element arranged between the bit line and the word line and turned on with a threshold voltage having a substantially identical absolute value with respect to either of positive and negative voltage application directions and a ferroelectric capacitor arranged between the bit line and the word line and serially connected to the switching element.
1. A ferroelectric memory comprising:
a bit line;
a word line arranged to intersect with said bit line; and
a memory cell including:
a switching element arranged between said bit line and said word line and turned on with a threshold voltage having a substantially identical absolute value with respect to either of positive and negative voltage application directions, and
a ferroelectric capacitor arranged between said bit line and said word line and serially connected to said switching element,
pulse application means for applying a pulse having a prescribed pulse width causing polarization inversion when a high voltage is applied to said ferroelectric capacitor while causing substantially no polarization inversion when a low voltage is applied to said ferroelectric capacitor of said memory cell, and
for applying a high voltage pulse having said prescribed pulse width to selected said memory cell while applying a low voltage pulse having said prescribed pulse width to non-selected said memory cell at least either in data writing or in data reading.
2. The ferroelectric memory according to claim 1 , wherein
said switching element includes a bidirectional diode.
3. A ferroelectric memory comprising:
a bit line;
a word line arranged to intersect with said bit line; and
a memory cell including:
a switching element arranged between said bit line and said word line and turned on with a threshold voltage having a substantially identical absolute value with respect to either of positive and negative voltage application directions, and
a ferroelectric capacitor arranged between said bit line and said word line and serially connected to said switching element,
wherein said switching element includes a bidirectional diode, and
wherein said bidirectional diode includes a Schottky diode.
4. The ferroelectric memory according to claim 3 , wherein
said Schottky diode is formed by joining a conductive layer and a semiconductor layer to each other, and
said conductive layer contains a metal and silicon while said metal includes at least one metal selected from a group consisting of Ir, Pt, Ru, Re, Ni, Co and Mo.
5. The ferroelectric memory according to claim 3 , wherein
said Schottky diode is formed by joining a conductive layer and a semiconductor layer to each other, and
said conductive layer contains a metal, nitrogen and silicon while said metal includes at least one metal selected from a group consisting of Ir, Pt, Ru, Re, Ni, Co and Mo.
6. A ferroelectric memory comprising:
a bit line;
a word line arranged to intersect with said bit line; and
a memory cell including:
a switching element arranged between said bit line and said word line and turned on with a threshold voltage having a substantially identical absolute value with respect to either of positive and negative voltage application directions, and
a ferroelectric capacitor arranged between said bit line and said word line and serially connected to said switching element,
wherein said switching element includes a bidirectional diode, and
wherein said bidirectional diode includes a p-n diode formed by joining a p-type semiconductor layer and an n-type semiconductor layer to each other.
7. The ferroelectric memory according to claim 6 , wherein
said p-type semiconductor layer and said n-type semiconductor layer forming said p-n diode are formed by amorphous layers.
8. A ferroelectric memory comprising:
a bit line;
a word line arranged to intersect with said bit line; and
a memory cell including:
a switching element arranged between said bit line and said word line and turned on with a threshold voltage having a substantially identical absolute value with respect to either of positive and negative voltage application directions, and
a ferroelectric capacitor arranged between said bit line and said word line and serially connected to said switching element,
wherein said switching element includes an MIM capacitor utilizing a tunnel current.
9. A ferroelectric memory comprising:
a memory cell including:
a ferroelectric capacitor connected to a gate portion of a field-effect transistor, and
a switching element serially connected to said ferroelectric capacitor and turned on with a threshold voltage having a substantially identical absolute value with respect to either of positive and negative voltage application directions,
pulse application means for applying a pulse having a prescribed pulse width causing polarization inversion when a high voltage is applied to said ferroelectric capacitor while causing substantially no polarization inversion when a low voltage is applied to said ferroelectric capacitor of said memory cell, and
for applying a high voltage pulse having said prescribed pulse width to selected said memory cell while applying a low voltage pulse having said prescribed pulse width to non-selected said memory cell at least either in data writing or in data reading.
10. The ferroelectric memory according to claim 9 , wherein
said switching element includes a bidirectional diode.
11. A ferroelectric memory comprising:
a memory cell including:
a ferroelectric capacitor connected to a gate portion of a field-effect transistor, and
a switching element serially connected to said ferroelectric capacitor and turned on with a threshold voltage having a substantially identical absolute value with respect to either of positive and negative voltage application directions,
wherein said switching element includes a bidirectional diode, and
wherein said bidirectional diode includes a Schottky diode.
12. The ferroelectric memory according to claim 11 , wherein
said Schottky diode is formed by joining a conductive layer and a semiconductor layer to each other, and
said conductive layer contains a metal and silicon while said metal includes at least one metal selected from a group consisting of Ir, Pt, Ru, Re, Ni, Co and Mo.
13. The ferroelectric memory according to claim 11 , wherein
said Schottky diode is formed by joining a conductive layer and a semiconductor layer to each other, and
said conductive layer contains a metal, nitrogen and silicon while said metal includes at least one metal selected from a group consisting of Ir, Pt, Ru, Re, Ni, Co and Mo.
14. A ferroelectric memory comprising:
a memory cell including:
a ferroelectric capacitor connected to a gate portion of a field-effect transistor, and
a switching element serially connected to said ferroelectric capacitor and turned on with a threshold voltage having a substantially identical absolute value with respect to either of positive and negative voltage application directions,
wherein said switching element includes a bidirectional diode, and
wherein said bidirectional diode includes a p-n diode formed by joining a p-type semiconductor layer and an n-type semiconductor layer to each other.
15. The ferroelectric memory according to claim 14 , wherein
said p-type semiconductor layer and said n-type semiconductor layer forming said p-n diode are formed by amorphous layers.
16. A ferroelectric memory comprising:
a memory cell including:
a ferroelectric capacitor connected to a gate portion of a field-effect transistor, and
a switching element serially connected to said ferroelectric capacitor and turned on with a threshold voltage having a substantially identical absolute value with respect to either of positive and negative voltage application directions,
wherein said switching element includes an MIM capacitor utilizing a tunnel current.
17. A method of operating a ferroelectric memory, the ferroelectric memory comprising a bit line, a word line arranged to intersect with said bit line, a memory cell including a switching element arranged between said bit line and said word line and turned on with a threshold voltage having a substantially identical absolute value with respect to either of positive and negative voltage application directions, and a ferroelectric capacitor arranged between said bit line and said word line and serially connected to said switching element, and pulse application means, the method comprising the steps of:
applying a pulse having a prescribed pulse width causing polarization inversion when a high voltage is applied to said ferroelectric capacitor while causing substantially no polarization inversion when a low voltage is applied to said ferroelectric capacitor to said memory cell, and
applying a high voltage pulse having said prescribed pulse width to selected said memory cell while applying a low voltage pulse having said prescribed pulse width to non-selected said memory cell at least either in data writing or in data reading.
18. A method of operating a ferroelectric memory, the ferroelectric memory comprising a memory cell including a ferroelectric capacitor connected to a gate portion of a field-effect transistor and a switching element serially connected to said ferroelectric capacitor and turned on with a threshold voltage having a substantially identical absolute value with respect to either of positive and negative voltage application directions, and pulse application means, the method comprising the steps of:
applying a pulse having a prescribed pulse width causing polarization inversion when a high voltage is applied to said ferroelectric capacitor while causing substantially no polarization inversion when a low voltage is applied to said ferroelectric capacitor of said memory cell, and
applying a high voltage pulse having said prescribed pulse width to selected said memory cell while applying a low voltage pulse having said prescribed pulse width to non-selected said memory cell at least either in data writing or in data reading.