Alignment pattern for a semiconductor device manufacturing process

1. An alignment pattern comprising: at least a sloped surface which communicates between a top surface of an inter-layer insulator extending over a surface of a substrate and a field oxide film selectively formed over said surface of said substrate and a flat surface of a metal plug having the flat surface and an inclined surface, and said flat surface being lower in level than said top surface of said inter-layer insulator, and said metal plug being buried within an alignment hole which completely penetrates said inter-layer insulator and at least reaches said field oxide film, so that said alignment hole has a bottom level which is deeper than a bottom level of said inter-layer insulator.

2. The alignment pattern as claimed in claim 1 , wherein said alignment hole completely penetrates not only said inter-layer insulator but also said field oxide film, so that said bottom level of said alignment hole is deeper than a bottom level of said field oxide film.

3. The alignment pattern as claimed in claim 1 , wherein said alignment hole has an aspect ratio which ensures that said at least sloped surface be remarkable even said at least sloped surface is obtained by a chemical mechanical polishing process for said metal plug.

4. The alignment pattern as claimed in claim 1 , wherein said at least sloped surface has a level-difference of not less than 200 nanometers.

5. The alignment pattern as claimed in claim 1 , wherein said field oxide film comprises an upper half portion above said surface of said substrate and a lower half portion below said surface of said substrate, and said lower half portion is thicker than said upper half portion.

6. The alignment pattern as claimed in claim 1 , wherein a majority part of said field oxide film is buried within said substrate.

7. The alignment pattern as claimed in claim 1 , wherein at least a most part of said field oxide film is buried within said substrate.

8. A semiconductor device including:

a substrate;

a field oxide film selectively formed over said substrate;

an inter-layer insulator extending over a surface of said substrate and said field oxide film;

an alignment hole which completely penetrates said inter-layer insulator and at least reaches said field oxide film, so that said alignment hole has a bottom level which is deeper than a bottom level of said inter-layer insulator; and

a metal plug buried within said alignment hole, said metal plug having a flat surface lower in level than a top surface of said inter-layer insulator and sloped surfaces serving as an alignment pattern which communicate between said top surface of said inter-layer insulator and said flat surface of said metal plug.

9. The semiconductor device as claimed in claim 8 , wherein said alignment hole completely penetrates not only said inter-layer insulator but also said field oxide film, so that said bottom level of said alignment hole is deeper than a bottom level of said field oxide film.

10. The semiconductor device as claimed in claim 8 , wherein said alignment hole has an aspect ratio which ensures that said at least sloped surface be remarkable even said at least sloped surface is obtained by a chemical mechanical polishing process for said metal plug.

11. The semiconductor device as claimed in claim 8 , wherein said at least sloped surface has a level-difference of not less than 200 nanometers.

12. The semiconductor device as claimed in claim 8 , wherein said field oxide film comprises an upper half portion above said surface of said substrate and a lower half portion below said surface of said substrate, and said lower half portion is thicker than said upper half portion.

13. The alignment pattern as claimed in claim 8 , wherein a majority part of said field oxide film is buried within said substrate.

14. The alignment pattern as claimed in claim 8 , wherein at least a most part of said field oxide film is buried within said substrate.

15. An alignment pattern comprising:

sloped surfaces of an interconnection layer extending both over a top surface of an inter-layer insulator and within an alignment hole, and said sloped surfaces being positioned over a periphery of said alignment hole, and said inter-layer insulator extending over a surface of a substrate and a field oxide film selectively formed over said surface of said substrate, and said alignment hole completely penetrating said inter-layer insulator and at least reaches said field oxide film, so that said alignment hole has a bottom level which is deeper than a bottom level of said inter-layer insulator,

wherein said interconnection layer directly contacts said substrate within said alignment hole.

16. The alignment pattern as claimed in claim 15 , wherein said alignment hole completely penetrates not only said inter-layer insulator but also said field oxide film, so that said bottom level of said alignment hole is deeper than a bottom level of said field oxide film.

17. The alignment pattern as claimed in claim 15 , wherein said alignment hole has an aspect ratio which ensures that said at least sloped surface be remarkable even said interconnection layer is re-flown.

18. An alignment pattern comprising:

sloped surfaces of an interconnection layer extending both over a top surface of an inter-layer insulator and within an alignment hole, and said sloped surfaces being positioned over a periphery of said alignment hole, and said inter-layer insulator extending over a surface of a substrate and a field oxide film selectively formed over said surface of said substrate, and said alignment hole completely penetrating said inter-layer insulator and at least reaches said field oxide film, so that said alignment hole has a bottom level which is deeper than a bottom level of said inter-layer insulator,

wherein said field oxide film comprises an upper half portion above said surface of said substrate and a lower half portion below said surface of said substrate, and said lower half portion is thicker than said upper half portion.

19. The alignment pattern as claimed in claim 15 , wherein a majority part of said field oxide film is buried within said substrate.

20. A semiconductor device including:

a substrate;

a field oxide film selectively formed over said substrate;

an inter-layer insulator extending over a surface of said substrate and said field oxide film;

an alignment hole which completely penetrates said inter-layer insulator and at least reaches said field oxide film, so that said alignment hole has a bottom level which is deeper than a bottom level of said inter-layer insulator; and

an interconnection layer extending both over said top surface of said inter-layer insulator and within said alignment hole, and said interconnection layer having sloped surfaces serving as an alignment pattern positioned over a periphery of said alignment hole,

wherein said interconnection layer directly contacts said substrate within said alignment hole.

21. The semiconductor device as claimed in claim 20 , wherein said alignment hole completely penetrates not only said inter-layer insulator but also said field oxide film, so that said bottom level of said alignment hole is deeper than a bottom level of said field oxide film.

22. The semiconductor device as claimed in claim 20 , wherein said alignment hole has an aspect ratio which ensures that said at least sloped surface be remarkable even said interconnection layer is re-flown.

23. A semiconductor device including:

a substrate;

a field oxide film selectively formed over said substrate;

an inter-layer insulator extending over a surface of said substrate and said field oxide film;

an alignment hole which completely penetrates said inter-layer insulator and at least reaches said field oxide film, so that said alignment hole has a bottom level which is deeper than a bottom level of said inter-layer insulator; and

an interconnection layer extending both over said top surface of said inter-layer insulator and within said alignment hole, and said interconnection layer having sloped surfaces serving as an alignment pattern positioned over a periphery of said alignment hole,

wherein said field oxide film comprises an upper half portion above said surface of said substrate and a lower half portion below said surface of said substrate, and said lower half portion is thicker than said upper half portion.

24. The semiconductor device as claimed in claim 20 , wherein a majority part of said field oxide film is buried within said substrate.

25. The alignment pattern of claim 1 , further comprising,

a metal layer that is directly on said top surface of said inter-layer insulator, said flat surface of said metal plug, and said sloped surface, and

a resist directly on said metal layer, wherein said resist has a opening therein that extends to said metal layer over said metal plug, and wherein said sloped surface extends around a periphery of said opening.

26. The semiconductor device of claim 8 , further comprising,

a metal layer that is directly on said top surface of said inter-layer insulator, said flat surface of said metal plug, and said sloped surfaces, and

a resist directly on said metal layer, wherein said resist has a opening therein that extends to said metal layer over said metal plug, and wherein said sloped surfaces extend around a periphery of said opening.

27. The alignment pattern of claim 15 , further comprising a resist directly on said interconnection layer, wherein said resist has a opening therein that extends to said interconnection layer over said alignment hole, and wherein said sloped surfaces extend around a periphery of said opening.

28. The semiconductor device of claim 20 , further comprising a resist directly on said interconnection layer, wherein said resist has a opening therein that extends to said interconnection layer over said alignment hole, and wherein said sloped surfaces extend around a periphery of said opening.