Copper alloy, array substrate of liquid crystal display using the same and method of fabricating the same
View Patent ↗A copper alloy for an electrical line of a liquid crystal display device that includes pure copper and an amount of indium.
1. A copper alloy for an electrical line of a liquid crystal display device that includes pure copper and an amount of indium, wherein the copper alloy has an electrical resistivity of about 3 to 4 μΩ·cm with annealing at a temperature of about 300 degrees centigrade.
2. The copper alloy according to claim 1 , wherein the amount of indium is within a range of about 0.1 to about 2.0 wt. %.
3. An array substrate for a liquid crystal display device, comprising:
a substrate;
a gate line and a data line on the substrate, the gate line and the data line crossing each other;
a thin film transistor electrically connected to the gate line and the data line; and
a pixel electrode electrically connected to the thin film transistor,
wherein the gate line includes a copper alloy having pure copper and an amount of indium, and wherein the copper alloy has an electrical resistivity of about 3 to 4 μΩ·cm with annealing at a temperature of about 300 degrees centigrade.
4. The array substrate according to claim 3 , wherein the amount of indium is within a range of about 0.1 to about 2.0 wt. %.
5. The array substrate according to claim 3 , wherein the data line includes a copper alloy having pure copper and an amount of indium.
6. The array substrate according to claim 5 , wherein the amount of indium is within a range of about 0.1 to about 2.0 wt. %.
7. The array substrate according to claim 3 , wherein the thin film transistor has source and drain electrodes that each include the copper alloy having the pure copper and the amount of indium.
8. The array substrate according to claim 7 , wherein the amount of indium is within a range of about 0.1 to about 2.0 wt. %.
9. An array substrate for a liquid crystal display device, comprising:
a substrate;
a gate line and a data line on the substrate, the gate line and the data line crossing each other;
a thin film transistor electrically connected to the gate line and the data line; and
a pixel electrode electrically connected to the thin film transistor,
wherein the data line includes a copper alloy having pure copper and an amount of indium, and wherein the copper alloy has an electrical resistivity of about 3 to 4 μΩ·cm with annealing at a temperature of about 300 degrees centigrade.
10. The array substrate according to claim 9 , wherein the amount of indium is within a range of about 0.1 to about 2.0 wt. %.
11. An array substrate for a liquid crystal display device, comprising:
a substrate;
a gate line and a data line on the substrate, the gate line and the data line crossing each other;
a thin film transistor electrically connected to the gate line and the data line, the thin film transistor includes a gate electrode and source and drain electrodes; and
a pixel electrode electrically connected to the thin film transistor,
wherein the gate line, the data line, the gate electrode, and source and drain electrodes each include a copper alloy having pure copper and an amount of indium, and wherein the copper alloy has an electrical resistivity of about 3 to 4 μΩ·cm with annealing at a temperature of about 300 degrees centigrade.
12. The array substrate according to claim 11 , wherein the amount of indium is within a range of about 0.1 to about 2.0 wt. %.
13. A method of fabricating an array substrate for a liquid crystal display device, comprising the steps of:
forming a gate line and a data line on a substrate, the gate line and the data line crossing each other;
forming a thin film transistor electrically connected to the gate line and the data line; and
forming a pixel electrode electrically connected to the thin film transistor,
wherein the gate line includes a copper alloy having pure copper and an amount of indium, and wherein the copper alloy has an electrical resistivity of about 3 to 4 μΩ·cm with annealing at a temperature of about 300 degrees centigrade.
14. The method according to claim 13 , wherein the amount of indium is within a range of about 0.1 to about 2.0 wt. %.
15. The method according to claim 13 , wherein the data line includes a copper alloy having pure copper and an amount of indium.
16. The method according to claim 13 , wherein the amount of indium is within a range of about 0.1 to about 2.0 wt. %.
17. The method according to claim 13 , wherein the step of forming a thin film transistor includes a step of forming source and drain electrodes that each including the copper alloy having the pure copper and the amount of indium.
18. The method according to claim 17 , wherein the amount of indium is within a range of about 0.1 to about 2.0 wt. %.