Method for fabricating an integrated semiconductor circuit
View Patent ↗A method for fabricating a semiconductor circuit uses a computer program to compute a circuit diagram that is made up of a large number of surface cells, each having a uniform height. Space-saving layouts require a uniform cell height for all the surface cells. The height is conventionally prescribed by a computer file containing standardized dimensions for a large number of surface cells. Accordingly, such surface cells as are required for a specific semiconductor circuit that is to be fabricated are selected, and the selection is used to compute a circuit-specific uniform cell height. The height is less than the height prescribed by the computer file and results in surface area being saved on the semiconductor chip.
1. A method for fabricating an integrated semiconductor circuit, which comprises the steps of:
using a computer program to define a circuit diagram by the steps of;
defining surface cells for different subcircuits in the integrated semiconductor circuit;
stipulating a circuit-specific uniform cell height by selecting from a set of the subcircuits having the surface cells for which a uniform cell height has been determined, the subcircuits needed for constructing the integrated semiconductor circuit and defining a least possible cell height of adequate size for all of the subcircuits selected as the circuit-specific uniform cell height for the surface cells in all the subcircuits selected;
disposing the surface cells selected in one plane;
computing interconnect paths between the surface cells selected; and
computing the circuit diagram from the surface cells selected and having the circuit-specific cell height;
fabricating the integrated semiconductor circuit on a basis of the circuit diagram;
defining a first doped well and a second doped well having an opposite doping to the first doped well in the circuit diagram for each of the subcircuits disposed in a surface cell, the first doped well and the second doped well in each of the surface cells being distanced from one another until the surface cells reach a height corresponding to the circuit-specific uniform cell height; and
defining a line of intersection defined between the first doped well and the second doped well in a subcircuit in the circuit diagram, and from the line of intersection the second doped well being shifted in a direction of increasing cell height.
2. The method according to claim 1 , which comprises computing for each of the subcircuits selected to construct the integrated semiconductor circuit, the least possible subcircuit-specific cell height individually and defining a greatest subcircuit-specific cell height as a lower limit for the circuit-specific uniform cell height for all the surface cells selected.
3. The method according to claim 1 , which comprises replacing the uniform cell height stipulated by a computer file for the surface cells by the circuit-specific uniform cell height having a lesser dimension.
4. The method according to claim 1 , which further comprises bridging interspaces arising as a result of the shifting of the p-wells in the circuit diagram by lengthening interconnects within the surface cells.
5. The method according to claim 1 , which further comprises forming the subcircuits provided in the surface cells as at least one component selected from the group consisting of logic gates, flip-flops and multiplexers.
6. The method according to claim 1 , which further comprises selecting no more than 50 to 150 of the subcircuits for which the circuit-specific uniform cell height is stipulated.
7. The method according to claim 1 , which further comprises fabricating the integrated semiconductor circuit based on the circuit diagram from no more than 1000 of the surface cells.
8. The method according to claim 1 , which further comprises fabricating the integrated semiconductor circuit as a logic circuit.