IP Library Granted Patent US 6,838,773
Granted Patent B2
US 6,838,773 · App. 10/311,707 · Granted Jan 4, 2005

Semiconductor chip and semiconductor device using the semiconductor chip

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Quick Facts
Patent No.
US 6,838,773
App. No.
10/311,707
Granted
Jan 4, 2005
Kind
B2
Abstract

A semiconductor chip of rewiring layer-integral type capable of preventing a maloperation by noise and a deterioration of communication characteristics and a semiconductor device with excellent communication characteristics; the semiconductor chip, wherein a rewiring layer ( 3 ) is formed on a circuit formed surface ( 1 a ) through an insulating layer ( 2 ) so as to form an antenna coil ( 4 ) with the rewiring layer ( 3 ), the antenna coil ( 4 ) is formed around the periphery of an analog circuit ( 21 ) on the circuit formed surface ( 1 a ) by avoiding forming on the analog circuit ( 21 ), the analog circuit ( 21 ) may be formed by collecting analog circuits to be formed in the semiconductor chip ( 1 A) therein, may be one of the particularly noise-susceptible analog circuits such as a power circuit, a calculation amplifier, a comparison amplifier, an RF receiving part, an RF transmitting part, an RF synthesizer part, and a voltage build-up circuit and an amplifying circuit forming a part of a memory part, or may be a coil provided in a part of the analog circuit formed in the semiconductor chip ( 1 A).

Claims (13)

1. A semiconductor chip having a rewiring layer superposed, through an insulating layer, on a circuit-formed region including a digital circuit and an analog circuit, said rewiring layer being formed integral with said chip, wherein all of or a part of said analog circuit susceptible to noise formed on said circuit-formed region and a wire forming said rewiring layer are arranged not to overlap each other through said insulating layer,

wherein bump-setting wires are formed by wires obtained from said rewiring layer, wherein said bump-setting wires are connected at one end to input/output terminals formed in said circuit-formed region and have bumps formed at the other end thereof.

2. A semiconductor chip having a rewiring layer superposed, through an insulating layer, on a circuit-formed region including a digital circuit and an analog circuit, said rewiring layer being formed integral with said chip, wherein a wire formed from said rewiring layer and at least one of noise-susceptible circuits formed on said circuit-formed region including a power circuit, an operational amplifier, a comparison amplifier, an RE receiving part, an RF transmitting part, and an RF synthesizer, are arranged not to overlap each other through said insulating layer,

wherein bump-setting wires are formed by wires obtained from said rewiring layer, wherein said bump-setting wires are connected at one end to input/output terminals formed in said circuit-formed region and have bumps formed at the other end thereof.

3. A semiconductor chip having a rewiring layer superposed, through an insulating layer, on a circuit-formed region including a digital circuit and an analog circuit, said rewiring layer being formed integral with said chip, wherein a noise-susceptible coil formed on said circuit-formed region and a wire formed from said rewiring layer are arranged not to overlap each other through said insulating layer.

4. A semiconductor chip according to claim 1 , wherein circuits formed in said circuit-formed region constitute a radio communication circuit formed by CMOS technology.

5. A semiconductor chip having a rewiring layer superposed, through an insulating layer, on a circuit-formed region including a digital circuit and an analog circuit, said rewiring layer being formed integral with said chip, wherein all of or a part of said analog circuit susceptible to noise formed on said circuit-formed region and a wire forming said rewiring layer are arranged not to overlap each other through said insulating layer,

wherein circuits formed in said circuit-formed region constitute a radio communication circuit for transmitting, receiving or exchanging signals of frequencies of 800 MHz or higher with an external device.

6. A semiconductor device having a semiconductor chip mounted on a substrate of predetermined dimensions and shape, wherein in said semiconductor chip, a rewiring layer is superposed on a circuit-formed region having a digital circuit and an analog circuit through an insulating layer and formed integral with said chip, and wherein a wire formed from said rewiring layer and all of or a part of said analog circuit susceptible to noise formed on said circuit-formed region are formed so as not to overlap each other through said insulating layer,

wherein bump-setting wires are formed by wires obtained from said rewiring layer, wherein said bump-setting wires are connected at one end to input/output terminals formed in said circuit-formed region and have bumps formed at the other end thereof.

7. A semiconductor device having a semiconductor chip mounted on a substrate of predetermined dimensions and shape, wherein in said semiconductor chip, a rewiring layer is superposed on a circuit-formed region having a digital circuit and an analog circuit through an insulating layer and formed integral with said chip, and wherein a wire formed from said rewiring layer and at least one of noise-susceptible circuits formed in said circuit-formed region, including a power circuit, an operational amplifier, a comparison amplifier, an RE receiving part, a transmitting part, and an RF synthesizer are arranged not to overlap each other through said insulating layer,

wherein bump-setting wires are formed by wires obtained from said rewiring layer, wherein said bump-setting wires are connected at one end to input/output terminals formed in said circuit-formed region and have bumps formed at the other end thereof.

8. A semiconductor device having a semiconductor chip mounted on a substrate of predetermined dimensions and size, wherein in said semiconductor chip, a rewiring layer is superposed on a circuit-formed region including a digital circuit and an analog circuit through an insulating layer and formed integral with said chip, and wherein a noise-susceptible coil formed in said circuit-formed region and a wire formed from said rewiring layer are arranged not to overlap each other through said insulating layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 19, 2009
From: HITACHI MAXELL, LTD.
To: KYUSHU HITACHI MAXELL, LTD.
Reel/Frame 022694/0568 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 19, 2002
From: KIKUCHI, YUJI; KISHIMOTO, KIYOSHARU; NAKAGAWA, KAZUNARI; HINO, YOSHIHARU
To: HITACHI MAXELL, LTD.
Reel/Frame 013817/0619 →