Nonvolatile memory with controlled voltage boosting speed
View Patent ↗In a nonvolatile memory in which a load on a boosting circuit changes according to the number of rewrite bytes, the boosting circuit is configured so as to perform voltage boosting at a relatively slow predetermined speed regardless of the number of rewrite bytes, whereby stress applied to each storage element is reduced and rewrite resistance is enhanced.
1. A nonvolatile memory, comprising:
a power terminal;
a ground terminal;
a plurality of nonvolatile storage elements;
a control circuit; and
a boosting circuit for boosting a power supply voltage supplied to the power terminal,
wherein a plurality of well regions are connected to back gates of the plurality of nonvolatile storage elements, a high voltage generated by the boosting circuit is applied to back gates of the nonvolatile storage elements to perform writing or erasing, and a magnitude of a load on the boosting circuit varies according to a number of the well regions to which the high voltage is applied upon erasing of each memory cell, and
wherein the boosting circuit is controlled so that, regardless of the number of well regions to which the high voltage is applied, a voltage boosting speed at erasure is approximately equal to a voltage boosting speed when the magnitude of the load is large.
2. A nonvolatile memory, comprising:
a power terminal;
a ground terminal;
a plurality of nonvolatile storage elements;
a control circuit; and
a boosting circuit for boosting a power supply voltage supplied to the power terminal,
wherein a plurality of well regions are connected to back gates of the plurality of nonvolatile storage elements, a high voltage, generated by the boosting circuit, is applied to back gates of the nonvolatile storage elements to perform writing or erasing, and a load on the boosting circuit changes according to a number of the well regions, based on a number of data, to which the high voltage is applied, and
wherein the boosting circuit is controlled so that, regardless of the number of data at erasure, a voltage boosting speed is approximately equal to a voltage boosting speed when the load is large.
3. The nonvolatile memory according to claim 2 , including a clock generator which generates a plurality of boosting clock signals different in frequency to operate the boosting circuit, and a counting circuit which counts the number of data at the writing or erasure, wherein the boosting circuit is supplied with a boosting clock signal having a frequency corresponding to a result of counting by the counting circuit, thereby controlling the voltage boosting speed.
4. The nonvolatile memory according to claim 2 , including a clock generator which generates a boosting clock signal for operating the boosting circuit, and a setting circuit for setting the frequency of the boosting clock signal generated by the clock generator, wherein the clock generator is configured so as to generate the boosting clock signal having a frequency corresponding to a value set to the setting circuit.
5. The nonvolatile memory according to claim 2 , including a clock generator which generates an internal clock signal for operating the control circuit, and a setting circuit for setting the frequency of the internal clock signal generated by the clock generator, wherein the clock generator is configured so as to generate the internal clock signal having a frequency corresponding to a value set to the setting circuit.
6. The nonvolatile memory according to claim 1 , wherein each of the storage elements has a gate electrode formed over a channel forming region lying between drain and source regions with a three-layered gate insulating film formed of an oxide film, a nitride film and an oxide film being interposed therebetween, and comprises a MOSFET having a MONOS structure wherein electrons or positive holes are accumulated in the nitride film to store information.
7. The nonvolatile memory according to claim 6 , wherein, of the storage elements connected to a same word line, one-byte storage elements adjacent to each other are formed on the same well region in the surface of a semiconductor substrate, and the respective well regions are configured so that different voltages are capable of being applied there to.
8. The nonvolatile memory according to claim 7 , wherein each of the storage elements has the well region to which a high voltage generated by the boosting circuit is applied when the electrons are injected into the nitride film.
9. The nonvolatile memory according to claim 8 , wherein each of the storage elements is configured such that the high voltage generated by the boosting circuit is applied to the gate electrode of each storage element of a word line selected upon the injection of the positive holes into the nitride film, and the high voltage is applied to a well region of each storage element connected to the same word line and subjected to non-selection, to thereby prevent the electrons or positive holes from being injected.
10. A method of controlling a nonvolatile memory having a power terminal, a ground terminal, a plurality of nonvolatile storage elements, a control circuit, and a boosting circuit for boosting a power supply voltage supplied to the power terminal, wherein a high voltage generated by the boosting circuit is applied to back gates of the nonvolatile storage elements to perform writing or erasing, and a load on the boosting circuit varies according to a number of data upon writing or erasing of each memory cell, comprising steps of:
counting the number of data at writing or erasure;
selecting a boosting clock signal, applied to the boosting circuit, according to the number of the data; and
controlling a voltage boosting speed so as to be approximately the same regardless of the number of the data.
11. The nonvolatile memory according to claim 2 , wherein each of the storage elements has a gate electrode formed over a channel forming region lying between drain and source regions with a three-layered gate insulating film formed of an oxide film, a nitride film and an oxide film being interposed therebetween, and comprises a MOSFET having a MONOS structure wherein electrons or positive holes are accumulated in the nitride film to store information.
12. The nonvolatile memory according to claim 11 , wherein of the storage elements connected to a same word line, one-byte storage elements adjacent to each other are formed on the same well region in the surface of a semiconductor substrate, and the respective well regions are configured so that different voltages are capable of being applied thereto.
13. The nonvolatile memory according to claim 12 , wherein each of the storage elements has the well region to which a high voltage generated by the boosting circuit is applied when the electrons are injected into the nitride film.
14. The nonvolatile memory according to claim 13 , wherein each of the storage elements is configured such that the high voltage generated by the boosting circuit is applied to the gate electrode of each storage element of a word line selected upon the injection of the positive holes into the nitride film, and the high voltage is applied to a well region of each storage element connected to the same word line and subjected to non-selection, to thereby prevent the electrons or positive holes from being injected.
15. A nonvolatile memory, comprising:
a power terminal;
a ground terminal;
a plurality of nonvolatile storage elements having back gates;
a plurality of well regions connected to the back gates;
a control circuit;
a boosting circuit to boost a power supply voltage supplied to the power terminal;
a clock generator to generate a plurality of boosting clock signals, each different in frequency, to operate the boosting circuit;
a counting circuit to count a number of data at writing or erasure; and
wherein:
a high voltage, generated by the boosting circuit, is applied to the back gates to perform writing or erasing,
a load on the boosting circuit changes according to a number of the well regions, based on the number of data, to which the high voltage is applied,
the boosting circuit is controlled so that, regardless of the number of data at erasure, a voltage boosting speed is approximately equal to a voltage boosting speed when the load is large,
the voltage boosting speed is externally changeable, and
the boosting circuit is supplied with a boosting clock signal having a frequency corresponding to a result of counting by the counting circuit, thereby controlling the voltage boosting speed.
16. The nonvolatile memory according to claim 1 , wherein the voltage boosting speed is externally changeable.
17. The nonvolatile memory according to claim 2 , wherein the voltage boosting speed is externally changeable.