Method and digital circuit for transmitting a plurality of bit sequences to be transmitted via several bus lines

1. A method for transmitting a multiplicity of bit sequences to be transmitted via a plurality of lines in which the bits of each bit-sequence are distributed across the plurality of lines and transmitted at the same instant, the method comprising:

determining at least one first bit-sequence combination with an increased bit-error probability when transmitted due to crosstalk between the lines across which the bit-sequence is distributed from the multiplicity of bit sequences to be transmitted;

converting, by using a mapping table, the first bit sequence combination into a second bit-sequence combination with a lower bit error probability;

generation of a separate conversion bit for each second bit-sequence combination that indicates that the second bit-sequence combination represents the converted first bit-sequence combination; and

transmitting the multiplicity of bit sequences having a second bit-sequence combination instead of the corresponding first bit-sequence combination, wherein the bits of the second bit-sequence combination are distributed across the plurality of lines and transmitted at the same instant and transmitting each associated conversion bit.

2. The method as claimed in claim 1 , further comprising:

applying one bit to each line at each transmission instant during transmission; and

forming the first bit-sequence combination and the second bit sequence combination by temporally successive bits, which are to be applied to the lines at successive transmission instants.

3. The method as claimed in claim 1 , in which the conversion bits are transmitted via a separate line dedicated to conversion bits.

4. The method as claimed in claim 1 , in which the conversion bits are temporally staggered in relation to the associated second bit sequence during transmission via the lines.

5. The method as claimed in one of claims 1 to 4 , in which the multiplicity of bit sequences with the second bit-sequence combination and the conversion bits are received via a plurality of lines and are processed in accordance with the following steps:

determining at least the second bit-sequence combination in the multiplicity of received bit sequences;

determining whether an associated conversion bit is present for the second bit-sequence combination, said conversion bit indicating that the determined second bit-sequence combination represents a converted first bit-sequence combination; and

converting the second bit-sequence combination into the first bit-sequence combination.

6. The method as claimed in claim 1 , wherein the method step of determining the at least one first bit-sequence combination with an increased bit-error probability when transmitted, is performed using a histogram.

7. A digital circuit arrangement for transmitting a multiplicity of bit sequences to be transmitted via a plurality of lines in which the bits of each bit-sequence are distributed across the plurality of lines and transmitted at the same instant, the arrangement comprising:

a bit-sequence determination unit for determining a first bit-sequence combination, having an increased bit-error probability when it is transmitted due to crosstalk between the lines across which the bit-sequence is distributed;

a bit-sequence conversion unit for converting the first bit-sequence combination into a second bit-sequence combination having lower bit-error probability using a mapping table and generating a separate conversion bit for every conversion, said conversion bit indicating that the associated second bit-sequence combination represents a converted first bit-sequence combination; and

a transmission unit for transmitting the bit-sequence combination, having the second bit-sequence combination instead of the corresponding first bit-sequence combination, wherein the bits of the second bit-sequence combination are distributed across the plurality of lines and transmitted at the same instant and transmitting the associated conversion bit.

8. The digital circuit arrangement as claimed in claim 7 , further comprising:

a plurality of bit lines which are connected to the transmission unit for transmitting the bit sequence to be transmitted.

9. A digital circuit arrangement for processing a multiplicity of received bit sequences via a plurality of lines in which the bits of each bit-sequence are distributed across the plurality of lines and transmitted at the same instant, further comprising:

a bit-sequence determination unit for determining at least one second bit-sequence combination in the multiplicity of received bit sequences using a mapping table in which at least one first bit-sequence combination, having increased bit-error probability when it is transmitted across the plurality of lines due to crosstalk between the lines has the second bit-sequence combination having lower bit-error probability associated with it when it is transmitted across the plurality of lines;

a conversion-bit determination unit for determining whether an associated separate conversion bit is present for every second bit-sequence combination which is determined, said conversion bit indicating that the determined second bit-sequence combination represents a converted first bit-sequence combination; and

a bit-sequence conversion unit for converting a determined second bit-sequence combination into the first bit-sequence combination.