IP Library › Granted Patent US 6,900,495
Granted Patent B2
US 6,900,495 · App. 10/314,049 · Granted May 31, 2005

Layer arrangement, memory cell, memory cell arrangement and method for producing a layer arrangement

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Quick Facts
Patent No.
US 6,900,495
App. No.
10/314,049
Granted
May 31, 2005
Kind
B2
Abstract

The invention relates to a layer arrangement, a memory cell, a memory cell arrangement and a method for producing a layer arrangement. The layer arrangement has a monocrystalline substrate, a highly doped region in the substrate and a metallically conductive structure in the highly doped region, a partial region of the highly doped region that is arranged in a surface region of the substrate being monocrystalline.

Claims (36)

1. A layer arrangement

having a monocrystalline substrate;

having a highly doped region in the substrate;

having a metallically conductive structure as buried interconnect in the highly doped region;

a partial region of the highly doped region that is arranged in a surface region of the substrate being monocrystalline.

2. The layer arrangement as claimed in claim 1 ,

which has a covering layer on the surface region of the substrate.

3. The layer arrangement as claimed in claim 1 or 2 ,

in which the highly doped region and the metallically conductive structure contained therein are arranged in a doped well region arranged in the substrate.

4. The layer arrangement as claimed in one of claims 1 to 3 ,

in which the substrate is a silicon substrate.

5. The layer arrangement as claimed in one of claims 1 to 4 ,

in which the metallically conductive structure comprises a metallic material.

6. The layer arrangement as claimed in one of claims 1 to 5 ,

in which the metallically conductive structure comprises silicide material.

7. The layer arrangement as claimed in claim 6 ,

in which the metallically conductive structure comprises

cobalt silicide and/or

tungsten silicide.

8. The layer arrangement as claimed in one of claims 2 to 7 ,

in which the covering layer is formed from monocrystalline material.

9. The layer arrangement as claimed in one of claims 2 to 8 ,

in which the covering layer is produced from silicon material.

10. The layer arrangement as claimed in one of claims 1 to 9 ,

having a transistor formed therein and/or thereon with a first and a second source/drain region, the first source/drain region being coupled to the metallically conductive structure.

11. The layer arrangement as claimed in claim 10 ,

in which the transistor is a vertical transistor.

12. The layer arrangement as claimed in claim 10 or 11 ,

having a capacitor formed therein and/or thereon, the capacitor being coupled to the second source/drain region of the transistor.

13. The layer arrangement as claimed in one of claims 1 to 12 ,

in which the highly doped region is laterally bounded in the substrate.

14. A memory cell

having a layer arrangement as claimed in one of claims 1 to 13 .

15. A memory cell arrangement having a plurality of memory cells as claimed in claim 14 .

16. The memory cell arrangement as claimed in claim 15 ,

which is formed as a dynamic RAM memory.