Array substrate for liquid crystal display device having redundancy line and fabricating method thereof
View Patent ↗An array substrate for a liquid crystal display device includes: a substrate; a gate line on the substrate; a gate insulating layer on the gate line; a data line on the gate insulating layer, the data line crossing the gate line; a data link line extending from the data line; a data pad connected to the data link line; a redundancy line adjacent to the data link line; a passivation layer covering the data link line, the data pad and the redundancy line, the passivation layer having a data link line contact hole exposing the data link line, first and second redundancy line contact holes exposing the redundancy line and a data pad contact hole exposing the data pad; a data pad terminal connected to the data pad through the data pad contact hole and to the redundancy line through the first redundancy line contact hole; a redundancy electrode connected to the redundancy line through the second redundancy line contact hole and to the data link line through the data link line contact hole; and a pixel electrode on the passivation layer.
1. An array substrate for a liquid crystal display device, comprising:
a substrate;
a gate line on the substrate;
a gate insulating layer on the gate line;
a data line on the gate insulating layer, the data line crossing the gate line;
a data link line extending from the data line;
a data pad connected to the data link line;
a redundancy line adjacent to the data link line;
a passivation layer covering the data link line, the data pad and the redundancy line, the passivation layer having a data link line contact hole exposing the data link line, first and second redundancy line contact holes exposing the redundancy line and a data pad contact hole exposing the data pad;
a data pad terminal connected to the data pad through the data pad contact hole and to the redundancy line through the first redundancy line contact hole;
a redundancy electrode connected to the redundancy line through the second redundancy line contact hole and to the data link line through the data link line contact hole; and
a pixel electrode on the passivation layer.
2. The array substrate according to claim 1 , wherein the substrate has an active region where images are displayed, a pad region on a periphery of the active region and a link region being a border between the active region and the pad region.
3. The array substrate according to claim 2 , wherein the gate line is disposed in the active region, the data link line is disposed in the link region and the data pad is disposed in the pad region.
4. The array substrate according to claim 1 , further comprising a thin film transistor connected to the gate line, the data line and the pixel electrode.
5. The array substrate according to claim 1 , wherein the data pad terminal and the redundancy electrode are made of the same material as the pixel electrode.
6. The array substrate according to claim 5 , wherein the data pad terminal, the redundancy electrode and the pixel electrode are made of a transparent conductive material.
7. The array substrate according to claim 1 , wherein the data link line and the data pad are made of the same material as the data line.
8. The array substrate according to claim 1 , wherein the redundancy line is made of the same material as the gate line.
9. The array substrate according to claim 8 , wherein the first and second redundancy line contact holes extend through the gate insulating layer to the redundancy line.
10. The array substrate according to claim 1 , wherein the redundancy line is made of the same material as the gate line.
11. The array substrate according to claim 1 , wherein the redundancy line has first and second connection portions, the data pad has a concave portion adjacent to the first connection portion and the data link line has a protruding portion adjacent to the second connection portion.
12. The array substrate according to claim 11 , wherein the first and second redundancy line contact holes and the data link line contact hole expose the first connection portion, the second connection portion and the protruding portion, respectively.
13. A fabricating method of an array substrate for a liquid crystal display device, comprising:
forming a gate line on a substrate;
forming a gate insulating layer on the gate line;
forming a data line on the gate insulating layer, the data line crossing the gate line;
forming a data link line extending from the data line;
forming a data pad connected to the data link line;
forming a redundancy line adjacent to the data link line;
forming a passivation layer covering the data link line, the data pad and the redundancy line, the passivation layer having a data link line contact hole exposing the data link line, first and second redundancy line contact holes exposing the redundancy line and a data pad contact hole exposing the data pad;
forming a data pad terminal connected to the data pad through the data pad contact hole and to the redundancy line through the first redundancy line contact hole;
forming a redundancy electrode connected to the redundancy line through the second redundancy line contact hole and to the data link line through the data link line contact hole; and
forming a pixel electrode on the passivation layer.
14. The method according to claim 13 , further comprising forming a thin film transistor connected to the gate line, the data line and the pixel electrode.
15. The method according to claim 13 , wherein the gate line is simultaneously formed with the redundancy line.
16. The method according to claim 13 , wherein the data pad terminal and the redundancy electrode are simultaneously formed with the pixel electrode.
17. The method according to claim 13 , wherein the data line, the data link line and the data pad are formed simultaneously of the same material.
18. A liquid crystal display device, comprising:
a lower substrate including:
a substrate,
a gate line on the substrate,
a gate insulating layer on the gate line,
a data line on the gate insulating layer, the data line crossing the gate line,
a data link line extending from the data line,
a data pad connected to the data link line,
a redundancy line adjacent to the data link line,
a passivation layer covering the data link line, the data pad and the redundancy line, the passivation layer having a data link line contact hole exposing the data link line, first and second redundancy line contact holes exposing the redundancy line and a data pad contact hole exposing the data pad,
a data pad terminal connected to the data pad through the data pad contact hole and to the redundancy line through the first redundancy line contact hole,
a redundancy electrode connected to the redundancy line through the second redundancy line contact hole and to the data link line through the data link line contact hole, and
a pixel electrode on the passivation layer;
an upper substrate having a common electrode; and
liquid crystal positioned between the upper and lower substrate.
19. The device according to claim 18 , wherein the substrate has an active region where images are displayed, a pad region on a periphery of the active region and a link region being a border between the active region and the pad region.
20. The device according to claim 19 , wherein the gate line is disposed in the active region, the data link line is disposed in the link region and the data pad is disposed in the pad region.