Multi-layer gate stack
View Patent ↗A method of making a semiconductor structure, comprises etching a nitride layer with a plasma to form a patterned nitride layer. The nitride layer is on a semiconductor substrate, a photoresist layer is on the nitride layer, and the plasma is prepared from a gas mixture comprising CF 4 and CHF 3 at a pressure of at least 10 mTorr.
1. A method of making a semiconductor structure, comprising:
etching a silicon nitride layer with a plasma to form a patterned nitride layer,
wherein the silicon nitride layer is on a gate layer comprising silicon,
the gate layer is on a semiconductor substrate,
a photoresist layer is on the silicon nitride layer,
the plasma is prepared from a gas mixture comprising CF 4 and CHF 3 at a pressure of at least 10 mTorr,
the photoresist layer comprises 193 nm photoresist, and
the patterned nitride layer has a line-edge roughness of at most 9 nm.
2. The method of claim 1 , wherein the gas mixture comprises a ratio by volume of CF 4 : CHF 3 of 10:1 to 1:3.
3. The method of claim 1 , wherein the pressure is 15–45 mTorr.
4. The method of claim 1 , wherein
the gas mixture comprises a ratio by volume of CF 4 : CHF 3 of 8:1 to 1:2, and
the pressure is 25–35 mTorr.
5. A method of making a semiconductor structure, comprising:
etching a silicon nitride layer with a plasma to form a patterned nitride layer,
wherein the silicon nitride layer is on a stack,
the stack is on a semiconductor substrate,
the stack comprises
(i) a gate layer, comprising silicon, and
(ii) a metallic layer, on the gate layer,
a photoresist layer is on the silicon nitride layer,
the photoresist layer comprises a 193 nm photoresist,
the patterned nitride layer has a line-edge roughness of at most 8 nm, and
the plasma comprises carbon, hydrogen and fluorine.
6. The method of claim 5 , wherein the patterned nitride layer has a line-edge roughness of at most 6 nm.
7. The method of claim 5 , wherein the plasma is prepared from a gas mixture at a pressure of at least 15 mTorr.
8. The method of claim 5 , wherein the plasma is prepared from a gas mixture at a pressure of 25–35 mTorr.
9. The method of claim 5 , wherein the gate layer comprises a P + region and an N + region, and
wherein the P + and N + regions are separated by a region which is on an isolation region of the substrate having a width of at most 0.4 microns.
10. A method of making a semiconductor device, comprising:
forming a semiconductor structure by the method of claim 1 , and
forming a semiconductor device from the semiconductor structure.
11. A method of making an electronic device, comprising:
forming a semiconductor device by the method of claim 10 , and
forming an electronic device comprising the semiconductor device.
12. A method of making a semiconductor device, comprising:
forming a semiconductor structure by the method of claim 5 , and
forming a semiconductor device from the semiconductor structure.
13. A method of making an electronic device, comprising:
forming a semiconductor device by the method of claim 12 , and
forming an electronic device comprising the semiconductor device.
14. The method of claim 1 , wherein a metallic layer is between the gate layer and the silicon nitride layer.
15. The method of claim 1 , wherein the silicon nitride layer has a thickness of at least 1100 angstroms.
16. The method of claim 1 , wherein the silicon nitride layer has a thickness of 1200–1400 angstroms.
17. The method of claim 5 , wherein the silicon nitride layer has a thickness of at least 1100 angstroms.
18. The method of claim 5 , wherein the silicon nitride layer has a thickness of 1200–1400 angstroms.
19. The method of claim 5 , wherein the plasma is prepared from a gas mixture consisting essentially of CF 4 and CHF 3 .
20. The method of claim 1 , wherein the gas mixture consists essentially of CF 4 and CHF 3 .