IP Library Granted Patent US 8,259,121
Granted Patent B2
US 8,259,121 · App. 10/314,525 · Granted Sep 4, 2012

System and method for processing data using a network

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Quick Facts
Patent No.
US 8,259,121
App. No.
10/314,525
Granted
Sep 4, 2012
Kind
B2
Abstract

Systems and methods are disclosed for video processing modules. More specifically a network is disclosed for processing data. The network comprises a register DMA controller adapted to support register access and at least one node adapted to the data. At least one link communicates with the node, and is adapted to transmit data and at least one network module communicates with at least the link, and is adapted to route data to at least the link.

Claims (54)

1. A network for processing data configured by a controller to form at least one display pipeline therein by dynamically selecting use of at least two selectable nodes from a plurality of selectable nodes and dynamically concatenating the selected at least two selectable nodes in the network together, wherein said at least one display pipeline has an independent data rate and a flow control module enables said independent data rate.

2. The network of claim 1 , wherein the network is further configured by said controller to form a plurality of display pipelines.

3. The network of claim 1 , further comprising at least two display pipelines having different data rates.

4. The network of claim 1 , further comprising a handshaking protocol configured to generate at least two display pipelines.

5. The network of claim 1 , wherein the network is further configured by said controller to change a functionality of said display pipeline by dynamically concatenating more than two nodes together.

6. The network of claim 1 , wherein said controller is a register DMA controller configured to support register access.

7. The network of claim 6 , wherein said register DMA controller is further configured to provide at least one instruction to form said display pipeline.

8. The network of claim 6 , wherein said register DMA controller is further configured to obtain at least one instruction from a register update list.

9. The network of claim 8 , wherein said register DMA controller is further configured to obtain said instruction in response to a trigger event.

10. A network for processing data comprising:

at least one display pipeline formed by dynamically selecting and concatenating at least two selectable nodes from a plurality of nodes, wherein the plurality of nodes are configured to process the data;

at least one network module configured to route the data by connecting the at least two selectable nodes using at least one link communicating between each of the at least two selectable nodes and the at least one network module; and

a register DMA controller for dynamically configuring the at least one display pipeline.

11. The network of claim 10 , wherein the network is further configured to form a plurality of display pipelines.

12. The network of claim 10 , comprising at least two display pipelines having different data rates.

13. The network of claim 10 , comprising at least one display pipeline having an independent data rate.

14. The network of claim 13 , further comprising a flow control module configured to enable said independent data rate.

15. The network of claim 10 , further comprising a handshaking protocol configured to generate at least two display pipelines.

16. The network of claim 10 , further comprising a plurality of network modules connecting at least two links and further configured to route information there between.

17. The network of claim 10 , further comprising a video register bus coupled to said register DMA controller.

18. The network of claim 17 further comprising a register bus connected to at least said register DMA controller, wherein said video register bus and register bus use identical protocol and signals.

19. The network of claim 18 , wherein said register DMA controller forwards all transactions to said video register bus.

20. The network of claim 10 , wherein said register DMA controller is configured to perform register DMA operations.

21. A method of processing data using a network comprising:

forming a first display pipeline using a register DMA controller to dynamically select at least two selectable nodes in the network;

processing the data using said first display pipeline;

forming a second display pipeline using said register DMA controller to dynamically select at least two selectable nodes in the network; and

processing the data using said second display pipeline, wherein said first and second display pipelines are different.

22. A method of processing data using a network comprising:

forming a display pipeline by using a register DMA controller to dynamically select and concatenate at least two selectable nodes from a plurality of nodes in the network, wherein at least one network module connects the at least two selectable nodes using at least one link between each of the at least two selectable nodes and the at least one network module; and

processing the data using said display pipeline.

23. The method of claim 22 , wherein forming said display pipeline comprises dynamically coupling a plurality of nodes together.

24. The method of claim 22 , further comprising starting said display pipeline at an entrance node.

25. The method of claim 22 further comprising ending said display pipeline at an exit node.

26. The method of claim 22 , further comprising adding functionality to said display pipeline by dynamically cascading at least one additional node to said at least two nodes.

27. A method of programming an A/V system using a network comprising:

(a) generating, at a video output, at least one trigger at an end of a first picture;

(b) obtaining at least one register update list from a main memory in response to receiving the at least one trigger;

(c) writing at least one register update entry from said at least one register update list to at least one register of a decoder to notify said decoder about said end of said first picture;

(d) configuring at least one node in the network for a second picture;

(e) enabling said at least one node;

(f) obtaining said second picture from a frame buffer; and

(g) providing said second picture to a display pipeline in the network.

28. The programming method of claim 27 comprising repeating steps (a)-(g).

29. The method of claim 27 , wherein said at least one node is an entry node.

30. The method of claim 27 , wherein said at least one node is a video feeder.

31. The network of claim 27 , comprising at least two display pipelines having different data rates.

32. The network of claim 27 , comprising at least one display pipeline having an independent data rate.

33. A network for processing data configured by a controller to form at least one display pipeline therein by dynamically selecting use of at least two selectable nodes from a plurality of selectable nodes and dynamically concatenating the selected at least two selectable nodes in the network together, wherein a handshaking protocol is configured to generate at least two display pipelines.

34. A network for processing data configured by a register DMA controller to form at least one display pipeline therein by dynamically selecting use of at least two selectable nodes from a plurality of selectable nodes and dynamically concatenating the selected at least two selectable nodes in the network together, wherein said register DMA controller is configured to support register access and to obtain at least one instruction from a register update list in response to a trigger event.

35. A system, comprising:

a controller that is operable to configure two or more nodes in a data processing network to form two or more display pipelines within said data processing network; and

a flow control module that is operable to configure each of said two or more display pipelines such that a corresponding data rate of each of said two or more display pipelines is independent of each other.

36. The system according to claim 35 , wherein said controller dynamically concatenates said two or more nodes in said data processing network to form said two or more display pipelines.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 09/05/2018 PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0133. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0456 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0133 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →