Very high speed arbitrary number of multiple signal multiplexer
View Patent ↗This invention provides a circuit and a method for very high-speed multiplexers. It provides a circuit that can produce an arbitrary number of multiple signal multiplexers. It also provides a circuit and a method which converts a parallel data bus into a serial data path. This invention contains an overlapped data generator, which takes in a data bus and outputs even and odd signals to a selective mux. It also contains a selective mux, which receives even and odd internal data bits from said overlapped data generator and which outputs one serial data bit. It also contains a phase locked loop/delay locked loop, PLL/DLL, which receives a set of phase clocks and which outputs five evenly-phase-distributed clock signals to a data select signal generator. Finally, the circuit includes a data select signal generator, which receives said five evenly-phase-distributed clock signals and which generates a ten-bit data select signal bus.
1. A very high speed arbitrary number of multiple signal multiplexer circuit comprising:
an overlapped data generator, which takes in n-bits of parallel data on an input data bus and outputs even and odd signals to a selective mux,
said selective mux, which receives even and odd internal data bits from said overlapped data generator and which outputs one single bit primary output,
a phase locked loop/delay locked loop, PLL/DLL, which receives a set of n-primary input phase clocks and which outputs n evenly-phase-distributed clock signals to a data select signal generator, and
said data select signal generator, which receives said n evenly-phase-distributed clock signals and which generates a ten-bit data select signal bus wherein said overlapped data generator, said selective mux, said phase locked loop/delay locked loop, and said data select generator are used to facilitate the time domain design of said multiple signal multiplexed circuit.
2. The very high speed arbitrary number of multiple signal multiplexed circuit of claim 1 wherein said overlapped data generator takes in n-bit bytes of data where ‘n’ equals the number of bits per byte.
3. The very high speed arbitrary number of multiple signal multiplexed circuit of claim 1 wherein said input data bus of said overlapped data generator has changing bytes every clock cycle.
4. The very high speed arbitrary number of multiple signal multiplexer circuit of claim 3 wherein said changing bytes on said input data bus of said overlapped data generator have even bytes distributed to an even byte output bus of said overlapped data generator.
5. The very high speed arbitrary number of multiple signal multiplexer circuit of claim 3 wherein said changing bytes on said input data bus of said overlapped data generator have odd bytes distributed to an odd byte output bus of said overlapped data generator.
6. The very high speed arbitrary number of multiple signal multiplexer circuit of claim 1 wherein said overlapped data generator's even byte bus data and said odd byte bus data have overlapping data valid times.
7. The very high speed arbitrary number of multiple signal multiplexer circuit of claim 1 wherein said phase-locked loop/delay-locked loop, PLL/DLL develops clocks, which are 1/n of the transmission data rate where n=number of bits in parallel.
8. The very high speed arbitrary number of multiple signal multiplexer circuit of claim 1 wherein said data select signal generator generates 2n data select lines whose active times overlap said adjacent data select lines' active times, where n equals the number of input bits to said data select signal generator.
9. The very high speed arbitrary number of multiple signal multiplexer circuit of claim 1 wherein said selective mux controls the serialization of said n-bits of even and odd data bits; into a single data out bit.
10. The very high speed arbitrary number of multiple signal multiplexer circuit of claim 9 wherein said n-bits of parallel data on said input data bus represent a simultaneous set of bits or packet of bits, which are active for a single clock cycle, or data byte transmission time.
11. The very high speed arbitrary number of multiple signal multiplexer circuit of claim 1 wherein said n-primary input phase clocks represent ‘n’ different phase clocks whose individual active times are non-overlapping and which occupy 1/n of said data byte transmission time.
12. The very high speed arbitrary number of multiple signal multiplexer circuit of claim 1 wherein said PLL/DLL utilizes the rising edge of time phase clock signals to eliminate any duty cycle requirements and allow very high-speed operation.
13. The very high speed arbitrary number of multiple signal multiplexer circuit of claim 1 wherein said single bit primary output contains n bits of serial data, which are contained in said single clock cycle or said data byte transmission time.
14. A method of developing a very high speed arbitrary number of multiple signal multiplexer circuit comprising the steps of:
providing an overlapped data generator, which takes in n-bits of parallel data on an input data bus and outputs even and odd signals to a selective mux,
providing said selective mux, which receives even and odd internal data bits from said overlapped data generator and which outputs one single bit primary output,
providing a phase locked loop/delay locked loop, PLL/DLL, which receives a set of n-primary input phase clocks and which outputs n evenly-phase-distributed clock signals to a data select signal generator, and
providing said data select signal generator, which receives said n evenly-phase-distributed clock signals and which generates a ten-bit data select signal bus wherein said overlapped data generator, said selective mux, said phase locked loop/delay locked loop, and said data select generator are used to facilitate the time domain design of said multiple signal multiplexer circuit.
15. The method of developing a very high speed arbitrary number of multiple signal multiplexer circuit of claim 14 wherein said overlapped data generator takes in n-bit bytes of data where ‘n’ equals the number of bits per byte.
16. The method of developing a very high speed arbitrary number of multiple signal multiplexer circuit of claim 14 wherein said input data bus of said overlapped data generator has changing bytes every clock cycle.
17. The method of developing a very high speed arbitrary number of multiple signal multiplexer circuit of claim 16 wherein said changing bytes on said input data bus of said overlapped data generator have even bytes distributed to an even byte output bus of said overlapped data generator.
18. The method of developing a very high speed arbitrary number of multiple signal multiplexer circuit of claim 16 wherein said changing bytes on said input data bus of said overlapped data generator have odd bytes distributed to an odd byte output bus of said overlapped data generator.
19. The method of developing a very high speed arbitrary number of multiple signal multiplexer circuit of claim 14 wherein said overlapped data generator's even byte bus data and said odd byte bus data have overlapping data valid times.
20. The method of developing a very high speed arbitrary number of multiple signal multiplexer circuit of claim 14 wherein said phase-locked loop/delay-locked loop, PLL/DLL develops clocks, which are 1/n of the transmission data rate where n=number of bits in parallel.
21. The method of developing a very high speed arbitrary number of multiple signal multiplexer circuit of claim 14 wherein said data select signal generator generates 2n data select lines whose active times overlap said adjacent data select lines' active times, where n equals the number of input bits to said data select signal generator.
22. The method of developing a very high speed arbitrary number of multiple signal multiplexer circuit of claim 14 wherein said selective mux controls the serialization of said n-bits of even and odd data bits; into a single data out bit.
23. The method of developing a very high speed arbitrary number of multiple signal multiplexer circuit of claim 22 wherein said n-bits of parallel data on said input data bus represent a simultaneous set of bits or packet of bits, which are active for a single clock cycle, or data byte transmission time.
24. The method of developing a very high speed arbitrary number of multiple signal multiplexer circuit of claim 14 wherein said n-primary input phase clocks represent ‘n’ different phase clocks whose individual active times are non-overlapping and which occupy 1/n of said data byte transmission time.
25. The method of developing a very high speed arbitrary number of multiple signal multiplexer circuit of claim 14 wherein said PLL/DLL utilizes the rising edge of time phase clock signals to eliminate any duty cycle requirements and allow very high speed operation.
26. The method of developing a very high speed arbitrary number of multiple signal multiplexer circuit of claim 14 wherein said single bit primary output contains n bits of serial data, which are contained in said single clock cycle or said data byte transmission time.