Programmable integrated circuit architecture
View Patent ↗A programmable logic device has a plurality of levels of programmable logic modules with fixed interconnections. The outputs of a level connect to inputs of the next level of programmable logic modules. The first level is fed from a bank of memory elements and the inputs to this bank of memory elements are derived from the last level. Crossbar switches are optionally inserted between a carefully chosen pairs of levels.
1. A programmable integrated circuit (IC) comprising:
a plurality of logic-level representations, wherein each logic-level representation comprises a plurality of programmable logic functions;
a first interconnect representation between adjacent logic-level representations;
a second interconnect representation coupled between a switch matrix and a third logic-level representation; and
a third interconnect representation coupled between the switch matrix and a fourth logic-level representation;
wherein the first interconnect representation couples to an output of a programmable logic function in a first logic-level representation to an input of a corresponding programmable logic function in the second logic-level representation that is adjacent to the first logic-level representation; and
wherein the third logic-level representation and the fourth logic-level representation are not adjacent.
2. A programmable integrated circuit (IC) comprising:
a plurality of logic-level representations, wherein each logic-level representation comprises a plurality of programmable logic functions;
a first interconnect representation between adjacent logic-level representations;
wherein the first interconnect representation couples an output of a programmable logic function in a first logic-level representation to an input of a corresponding programmable logic function in a second logic-level representation that is adjacent to the first logic-level representation;
a first memory block comprising an output of the first programmable logic function of the first logic-level representation and an output the second programmable logic function of the first logic-level representation; and
a second memory block comprising an output of the third programmable logic function of a second logic-level representation and an output of the fourth programmable logic function of the second logic level representation;
wherein within the first memory block the output of the first programmable logic function of the first logic-level representation corresponds to the output of the second programmable logic function of the first logic-level representation, and within the second memory block the output of the third programmable logic function of the second logic-level representation corresponds to the output of the fourth programmable logic function of the second logic-level representation;
wherein the output of the first programmable logic function of the first logic-level representation of the first memory block is coupled to the output of the third programmable logic function and the output of the fourth programmable logic function of the second logic-level representation of the second memory block, and the output of the first programmable logic function of the first logic-level representation is uncoupled to the output of the second programmable logic function of the first logic-level representation within the first memory block; and
wherein the output of the third programmable logic function of the second logic-level representation of the second memory block is coupled to the output of the first programmable logic function and to the output of the second programmable logic function of the first logic-level representation of the first memory block, and the output of the third programmable logic function of the second logic-level representation is uncoupled to the output of the fourth programmable logic function of the second logic-level representation within the second memory block.
3. A programmable integrated circuit (IC), comprising:
a plurality of logic-level representations, wherein each logic-level representation comprises a plurality of programmable logic functions;
a first interconnect representation between adjacent logic-level representations;
wherein the first interconnect representation couples an output of a programmable logic function in a first logic-level representation to an input of a corresponding programmable logic function in a second logic-level representation that is adjacent to the first logic-level representation;
a third logic-level representation comprises of programmable logic functions; and
an interconnect representation between the first logic-level representation and the third logic-level representation;
wherein the interconnect representation couples an output of a programmable logic function in the first logic-level representation to an input of a corresponding programmable logic function in a third logic-level representation;
wherein there is no interconnect representation couples an output of a programmable logic function in the first logic-level to an input of corresponding programmable logic function in a fourth logic-level representation; and
wherein there is no interconnect representation couples an output of programmable logic function in the second logic-level representation to an input of a corresponding programmable logic function in the third logic-level representation.
4. An electronic design method comprising the steps of:
generating a plurality of logic-level representations;
wherein each logic-level representation comprises a plurality of programmable logic functions;
generating a first interconnect representation between adjacent logic-level representations;
wherein the first interconnect representation couples an output of a programmable logic function in a first logic-level representation to an input of a corresponding programmable logic function in a second logic-level representation that is adjacent to the first logic level representation;
generating a second interconnect representation coupled between a switch matrix and a third logic-level representation; and
generating a third interconnect representation coupled between the switch matrix and a fourth logic-level representation;
wherein the third logic-level representation and the fourth logic-level representation are not adjacent.
5. An electronic design method comprising the steps of:
generating a plurality of logic-level representations, wherein each logic-level representation comprises a plurality of programmable logic functions;
generating a first interconnect representation between adjacent logic-level representations;
wherein the first interconnect representation couples an output of a programmable logic function in a first logic-level representation to an input of a corresponding programmable logic function in a second logic-level representation that is adjacent to the first logic level representation;
generating a first memory block comprises an output of the first programmable logic function of a first logic-level representation and an output the second programmable logic function of the first logic level representation; and
generating a second memory block comprises an output of the third programmable logic function of a second logic-level representation and an output of the fourth programmable logic function of the second logic level representation;
wherein within the first memory block the output of the first programmable logic function of the first logic-level representation corresponds to the output of the second programmable logic function of the first logic-level representation, and within the second memory block the output of the third programmable logic function of the second logic-level representation corresponds to the output of the fourth programmable logic function of the second logic-level representation;
wherein the output of the first programmable logic function of the first logic-level representation of the first memory block is coupled to the output of the third programmable logic function and to the output of the fourth programmable logic function of the second logic-level representation of the second memory block, and the output of the first programmable logic function of the first logic-level representation is uncoupled to the output of the second programmable logic function of the first logic-level representation within the first memory block; and
wherein the output of the third programmable logic function of the second logic-level representation of the second memory block is coupled to the output of the first programmable logic function and to the output of the second programmable logic function of the first logic-level representation of the first memory block, and the output of the third programmable logic function of the second logic-level representation is uncoupled to the output of the fourth programmable logic function of the second logic-level representation within the second memory block.
6. An electronic design method comprising the steps of:
generating a plurality of logic-level representations, wherein each logic-level representation comprises a plurality of programmable logic functions;
generating a first interconnect representation between adjacent logic-level representations;
wherein the first interconnect representation couples an output of a programmable logic function in a first logic-level representation to an input of a corresponding programmable logic function in a second logic-level representation that is adjacent to the first logic-level representation;
generating a third interconnect representation comprises of programmable logic functions; and
generating an interconnect representation between the first logic-level representation and the third logic-level representation;
wherein the interconnect representation couples an output of a programmable logic function in a first logic-level representation to an input of a corresponding programmable logic function in a third logic-level representation;
wherein there is no interconnect representation couples an output of a programmable logic function in the first logic-level to an input of corresponding programmable logic function in a second logic-level representation; and
wherein there is no interconnect representation couples an output of a programmable logic function in the second logic-level representation to an input of a corresponding programmable logic function in the third logic-level representation.