Hierarchically-controlled automatic test pattern generation
View Patent ↗Hierarchically-controlled automatic test pattern generation (ATPG) is provided. One embodiment comprises a method for automatically generating test patterns for testing a device under test. Briefly described, one such method comprises the steps of: receiving a hierarchical model of a device under test, the hierarchical model comprising at least one low-level design component and at least one high-level design component which contains the low-level design component; selecting a fault to be detected in the device under test; and performing an automatic test pattern generation (ATPG) algorithm on the design components based on the hierarchy of the hierarchical model.
1. A method for automatically generating test patterns for testing a device under test, the method comprising the steps of:
receiving a hierarchical model of a device under test, the hierarchical model comprising at least one child block and at least one parent block which contains the child block; and
performing an automatic test pattern generation (ATPG) process on the at least one child block and the at least one parent block via a post-order traversal of the hierarchical model.
2. The method of claim 1 , wherein the step of performing an automatic test pattern generation (ATPG) process on the at least one child block and the at least one parent block via a post-order traversal of the hierarchical model comprises incorporating the result of the ATPG process on the at least one child block when performing the ATPG process on the at least one parent block.
3. The method of claim 1 , wherein the step of performing an ATPG process comprises the steps of:
generating a test pattern that detects at least one fault for the at least one child block;
designating the at least one fault as detected; and
promoting the at least one fault and the test pattern to the parent block containing the at least one child block.
4. The method of claim 3 , wherein the step of performing an ATPG process comprises restricting access to at least one primary input and at least one primary output of the at least one child block.
5. The method of claim 4 , wherein the restricting access comprises defining a fixed value for at least one primary input.
6. The method of claim 3 , wherein the step of generating a test pattern that detects at least one fault is based only on scan registers.
7. The method of claim 1 , wherein the step of performing an ATPG process comprises the steps of:
determining that a fault is untestable on the at least one child block; and
promoting the untestable fault to the parent block containing the at least one child block.
8. The method of claim 7 , wherein the step of performing an ATPG process comprises accessing all of the primary inputs and primary outputs of the at least one child block.
9. A program embodied in a computer-readable medium for automatically generating test patterns for a device under test, the program comprising:
logic configured to access a hierarchical model of a device under test, the hierarchical model comprising at least one child block and at least one parent block which contains the child block; and
logic configured to initiate an automatic test pattern generation (ATPG) process on the at least one child block and the at least one parent block via a post-order traversal of the hierarchical model.
10. The program of claim 9 , wherein the logic configured to initiate an ATPG process comprises logic configured to incorporate the result of the ATPG process on the at least one child block when performing the ATPG process on the at least one parent block.
11. The program of claim 9 , wherein the logic configured to initiate an ATPG process comprises:
logic configured to generate a test pattern that detects at least one fault for the at least one child block;
logic configured to designate the at least one fault as detected; and
logic configured to promote the at least one fault and the test pattern to the parent block containing the at least one child block.
12. The program of claim 11 , wherein the logic configured to initiate an ATPG process comprises logic configured to prevent the ATPG process from accessing at least one primary input and at least one primary output of the at least one child block.
13. The program of claim 12 , wherein the logic configured to prevent the ATPG process from accessing at least one primary input and at least one primary output comprises logic configured to define the value of at least one primary input as unknown.
14. The program of claim 11 , wherein the logic configured to generate a test pattern that detects at least one fault further comprises logic configured to generate the test pattern based only on scan registers.
15. The program of claim 9 , wherein the logic configured to initiate an ATPG process comprises:
logic configured to determine that a fault is untestable on the at least one child block; and
logic configured to promote the untestable fault to the parent block containing the at least one child block.
16. The program of claim 15 , wherein the logic configured to initiate an ATPG process comprises logic configured to enable the ATPG process to access all of the primary inputs and primary outputs of the at least one child block.
17. The program of claim 15 , further comprising the hierarchical model.
18. The program of claim 15 , further comprising the logic for performing the ATPG process.
19. An automatic test pattern generation system comprising:
a memory containing a hierarchical model of a device under test, the hierarchical model comprising at least one child block and at least one parent block which contains the child block; and
a processor device configured to perform an automatic test pattern generation (ATPG) process on the at least one child block and the at least one parent block via a post-order traversal of the hierarchical model.
20. The automatic test pattern generation system of claim 19 , wherein the processor device is further configured to incorporate the result of the ATPG process on the at least one child block when performing the ATPG process on the at least one parent block.
21. The automatic test pattern generation system of claim 19 , wherein the processor device is further configured to:
generate a test pattern that detects at least one fault for the at least one child block;
designate the at least one fault as detected; and
promote the at least one fault and the test pattern to the parent block containing the at least one child block.
22. The automatic test pattern generation system of claim 21 , wherein the processor device is further configured to prevent the ATPG process from accessing at least one primary input and at least one primary output of the at least one child block.
23. The automatic test pattern generation system of claim 22 , wherein the processor is further configured to prevent the ATPG process from accessing at least one primary input and at least one primary output by at least one of the following:
fixing the value of at least one primary input; and
defining at least one primary input to an unknown value.
24. The automatic test pattern generation system of claim 21 , wherein the processor device is further configured to generate the test pattern based only on scan registers.
25. The automatic test pattern generation system of claim 19 , wherein the processor device is further configured to:
determine that a fault is untestable on the at least one child block; and
promote the untestable fault to the parent block containing the at least one child block.
26. The automatic test pattern generation system of claim 25 , wherein the processor device is further configured to enable the ATPG process to access all of the primary inputs and primary outputs of the at least one child block.
27. An automatic test pattern generation system comprising:
means for storing a hierarchical model of a device under test, the hierarchical model comprising at least one child block and at least one parent block which contains the child block; and
means for performing an automatic test pattern generation (ATPG) process on the at least one child block and the at least one parent block via a post-order traversal of the hierarchical model.