IP Library Granted Patent US 39,283
Granted Patent E1
US 39,283 · App. 10/322,081 · Granted Sep 12, 2006

Method for selective filtering

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Quick Facts
Patent No.
US 39,283
App. No.
10/322,081
Granted
Sep 12, 2006
Kind
E1
Abstract

A method for digital clock recovery and selective filtering includes prescribing or calculating first coefficients of a prototype of a selective filter at a characteristic frequency fc for a given sampling frequency fa. Second coefficients of a selective filter are calculated at the characteristic frequency fc 2 from the first coefficients at points t k =Δt+k*d, where k is an integer greater than or equal to 0, by interpolating values of a continuous-time impulse response at points t k , where d = fc2 * fa fc * fa 1 The selective filter is operated with the second coefficients at fa 1 .

Claims (75)

1. A method for selective filtering, which comprises:

simulating different selective filters with a coefficient and filter calculation unit, a phase detector, a loop filter, and a digital oscillator depending on sets of first and second coefficients used for filter calculation;

determining a first set of coefficients of a prototype of a further selective filter at a characteristic frequency fc for a given sampling frequency fa;

calculating a second set of coefficients of the further selective filter at a characteristic frequency fc2 from the first coefficients at points t k =Δt+k*d, where k=0, 1, . . . , the further selective filter to be operated at a sampling rate fa 1 , by interpolating values of a continuous-time impulse response of a simulation of the further selective filter at point t k , where

d

=

fc2

*

fa

fc

*

fa

1

;

emulating the further selective filter with the second coefficients using the coefficient and filter calculation unit, the phase detector, the loop filter, and the digital oscillator; and

operating the further selective filter at the sampling rate fa 1 .

2. The method according to claim 1 , which further comprises performing the determining step by prescribing the first set of coefficients of a prototype of a further selective filter at a characteristic frequency fc for a given sampling frequency fa.

3. The method according to claim 1 , which further comprises performing the determining step by calculating the first set of coefficients of a prototype of a further selective filter at a characteristic frequency fc for a given sampling frequency fa.

4. The method according to claim 1 , which further comprises utilizing output values I0+k*ΔI with the digital oscillator while using the output values I0+K*ΔI for calculating Δt+k*d, where ΔI is an increment provided by the digital oscillator and I0 is the start value after an overflow of the digital oscillator.

5. The method according to claim 1 , which further comprises:

using an output value of the digital oscillator after an overflow I0, multiplied by the constant

r

=

fa

*

fc2

fc

*

fa2

,

for generating a start value Δt for an interpolation of the second set of coefficients based on a data signal, where fa2 represents a sampling frequency at which the data signal is interpolated in order to selectively filter a sampled data signal.

6. The method according to claim 1 , which further comprises using an overflowing accumulator as the digital oscillator.

7. The method according to claim 6 , which further comprises feeding the accumulator with an increment formed by adding an output signal of the loop filter to a value defining an idle frequency of the digital oscillator for generating the output value of the digital oscillator.

8. The method according to claim 1 , which further comprises:

feeding an input signal to arithmetic units operating in parallel, each of the arithmetic units calculating a future output value of a selective filter, and

selecting, in the event of an overflow of the digital oscillator, an output value of an arithmetic unit having already finished a calculation at the time of the overflow for generating a selectively filtered sampled data signal.

9. The method according to claim 8 , which further comprises defining a number N of arithmetic units operating in parallel based on a number K of coefficients of the selective filter simulated respectively by the coefficient and filter calculation unit, the phase detector, the loop filter, and the digital oscillator, according to the following conditions:

N

>=

K

·

fc

·

fa2

fa

·

fc2

,

where N is an integer.

10. The method according to claim 8 , which further comprises:

utilizing modulo-N counter for selecting the arithmetic units;

cyclically addressing the arithmetic units with the modulo-N counter; and

incrementing the modulo-N counter with each overflow of the digital oscillator.

11. The method according to claim 10 , which further comprises:

resetting an accumulator in each arithmetic unit if the arithmetic unit is addressed;

loading the arithmetic unit with an output value of the digital oscillator after the overflow of the digital oscillator;

storing an instantaneous increment value of the digital oscillator;

accumulating the instantaneous increment value for each sampling clock of the input signal;

scaling an output value of the accumulator with a value

r

=

fa

*

fc2

fc

*

fa2

for each input clock pulse, where fa2 represents a sampling frequency at which the data signal is interpolated for selectively filtering a sample data signal.

12. The method according to claim 11 , which further comprises defining, with a scaled output value of the accumulator, a position at which a second coefficient must be interpolated from the first coefficient of the prototype at this distinct position for the further selective filter.

13. The method according to claim 1 , which further comprises:

providing a single coefficient calculation unit;

calculating the second set of coefficients sequentially in time with the single coefficient calculation unit;

calculating the filter output values sequentially in time in a multiplier and splitting the filter output values between N accumulators; and

selectively storing the respective input values in N further accumulators.

14. The method according to claim 13 , wherein the respective input values are an increment and output value of the digital oscillator.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2022
From: INTEL DEUTSCHLAND GMBH
To: INTEL CORPORATION
Reel/Frame 061356/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2012
From: INTEL MOBILE COMMUNICATIONS TECHNOLOGY GMBH
To: INTEL MOBILE COMMUNICATIONS GMBH
Reel/Frame 027556/0709 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 18, 2012
From: INFINEON TECHNOLOGIES AG
To: INTEL MOBILE COMMUNICATIONS TECHNOLOGY GMBH
Reel/Frame 027548/0623 →