Multi-processing memory duplication system

1. An apparatus comprising:

a first processor module;

a second processor module;

a bus coupled to the first processor module and the second processor module,

wherein the bus is configured to transmit both processor related communication and memory related communication and wherein:

the first processor module comprises a first processing unit, a first memory controller/host bridge, a first PCI-to-PCI bridge, a first memory replication engine and a first memory unit; and

the second processor module comprises a second processing unit, a second memory controller/host bridge, a second PCI-to-PCI bridge, a second memory replication engine and a second memory unit,

wherein the first PCI-to-PCI bridge, the second PCI-to-PCI bridge, the first memory replication engine, and the second memory replication engine are mutually coupled by the bus,

the first memory controller/host bridge coupled to the first memory replication engine and the first memory unit,

the second memory controller/host bridge coupled to the second memory replication engine and the second memory unit,

the first memory controller/host bridge coupled to the first PCI-to-PCI bridge,

the second memory controller/host bridge coupled to the second PCI-to-PCI bridge,

the first memory controller/host bridge coupled to the first processing unit, and

the second memory controller/host bridge coupled to the second processing unit.

2. A multi-processing system comprising:

an active processor module having a first processing unit, a first memory, a first memory controller/host bridge to control read/write to the first memory and a first memory dupication engine to duplicate a predetermined region of the first memory;

a non-active processor module having a second processing unit, a second memory, a second memory controller/host bridge to control read/write to the second memory and a second memory dupication engine to store the duplicated data; and

a first PCI-to-PCI bridge and a second PCI-to-PCI bridge coupled by a first bus to interface the active processor module and the non-active processor module, and to transmit the duplicated data of the predetermined region to the non-active processor module, the first PCI-to-PCI bridge, the second PCI-to-PCI bridge, the first memory duplication engine and the second memory duplication engine each being coupled to the first bus.

3. The system of claim 2 , wherein the first memory duplication engine is coupled to a second bus between the first memory controller/host bridge and the first memory, and the first memory duplication engine to replicate real time data and to transmit the data to the second PCI-to-PCI bridge of the non-active processor module.

4. The system of claim 3 , wherein the first memory duplication engine performs the duplication of the data in real time when the active processor module is activated.

5. The system of claim 2 , wherein the first memory controller/host bridge is coupled to the first PCI-to-PCI bridge by a PCI bus to read/write the data from the first memory.

6. The system of claim 2 , wherein the first memory controller/host bridge includes a direct memory access (DMA) engine to directly read/write the data of the predetermined region from the first memory.

7. The system of claim 6 , wherein the DMA engine reads the data from the first memory, converts an address, and transmits the data across the first bus to the second PCI-to-PCI bridge of the non-active processor module.

8. The system of claim 2 , wherein the second memory controller/host bridge includes a direct memory access (DMA) engine to read data from a predetermined region of the second memory of the non-active processor module, and to replicate an image of the read data onto the first memory of the active processor module.

9. A multi-processing system comprising:

first and second processor modules having first and second processing units for performing control and data processes, first and second memory controller/host bridges to control memory and to directly access data, and first and second memories;

first and second memory duplication engines to duplicate data and to transmit the duplicated data to the other processor module after monitoring, in real time, the data being stored in the first memory of the first processor module; and

a first PCI-to-PCI bridge and a second PCI-to-PCI bridge to allow communication between the first and second processor modules and to transmit the data duplicated by the first memory duplication engine to the second memory controller/host bridge of the second processor module, the first PCI-to-PCI bridge, the second PCI-to-PCI bridge, the first memory duplication engine and the second memory duplication engine each being coupled to a first PCI bus.

10. The system of claim 9 , wherein each of the first and second memory controller/host bridges includes a direct memory access (DMA) engine to directly access a memory and to access data of a specific region of the memory.

11. The system of claim 10 , wherein the first memory controller/host bridge of the first processor module performs high speed duplication of the data of the specific region in the first memory using the DMA engine, and the first memory controller/host bridge to transmit the data to the second PCI-to-PCI bridge of the second processor module through the first PCI-to-PCI bridge.

12. The system of claim 10 , wherein the first memory controller/host bridge of the first processor module acquires the data of the specific region from the DMA engine of the second memory controller/host bridge by receiving an image of data of a partial region in the second memory and performing an identity proving.

13. The system of claim 9 , wherein the first memory duplication engine and the first PCI-to-PCI bridge of the first processor module are coupled to a PCI master interface unit.

14. The system of claim 9 , wherein the first memory controller/host bridge is coupled to the first PCI-to-PCI bridge by a second PCI bus.

15. The system of claim 9 , wherein the first memory duplication engine of the first processor module comprises:

a memory bus interface unit to monitor the first memory through a memory bus;

a page mode controller to manage page information regarding the first memory;

an address restoration unit to restore an actual address based on data address and control signals received through the memory bus interface unit;

a duplication filtering unit to determine whether data is duplicated based on the restored address;

a buffer to store the data to be duplicated;

a buffer manager to store the restored address and the data received through the memory bus interface unit and to manage a current status of the buffer;

a PCI back end unit to read the data and address from the buffer; and

a PCI master interface unit to transmit the data as read at the PCI back end to the second PCI-to-PCI bridge.