IP Library Granted Patent US 6,869,853
Granted Patent B1
US 6,869,853 · App. 10/323,002 · Granted Mar 22, 2005

Fabrication of a bipolar transistor using a sacrificial emitter

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Quick Facts
Patent No.
US 6,869,853
App. No.
10/323,002
Granted
Mar 22, 2005
Kind
B1
Abstract

In one embodiment, a transistor is fabricated by forming a sacrificial emitter over a base, forming an oxide layer over the sacrificial emitter, removing a portion of the oxide layer, and then removing the sacrificial emitter. An emitter is later formed in the space formerly occupied by the sacrificial emitter. The sacrificial emitter allows a base implant step to be performed early in the process using a single masking step. The base may comprise epitaxial silicon-germanium or silicon.

Claims (43)

1. A method of fabricating a bipolar transistor, the method comprising:

forming a sacrificial emitter over a base;

forming a first oxide layer over the sacrificial emitter;

forming a masking material over the first oxide layer;

planarizing the masking material to expose the first oxide layer;

etching a portion of the first oxide layer over the sacrificial emitter; and

removing the sacrificial emitter.

2. The method of claim 1 wherein the base comprises silicon-germanium (SiGe).

3. The method of claim 1 wherein the sacrificial emitter comprises:

a polysilicon material over a second oxide layer.

4. The method of claim 1 further comprising:

after forming the sacrificial emitter but prior to forming the first oxide layer, implanting a dopant in an extrinsic base region.

5. The method of claim 1 wherein the base comprises silicon.

6. The method of claim 1 wherein removing the sacrificial emitter comprises:

etching the sacrificial emitter using a second oxide layer as an etch stop; and

etching the second oxide layer to expose the base.

7. The method of claim 1 further comprising:

forming a polysilicon material on the base.

8. The method of claim 1 wherein forming the masking material over the first oxide layer comprises spin-coating a photoresist material.

9. The method of claim 1 wherein planarizing the masking material comprises performing an etch-back process.

10. A method of forming a bipolar transistor, the method comprising:

implanting a dopant in a silicon-germanium (SiGe) layer that is under a sacrificial emitter;

depositing a first oxide layer over the sacrificial emitter;

forming a mask over the first oxide layer:

isotropically etching the first oxide layer to create an undercut under the mask and fully expose a top portion of the sacrificial emitter; and

replacing the sacrificial emitter with an emitter.

11. The method of claim 10 wherein replacing the sacrifical emitter with an emitter comprises:

etching the sacrificial emitter to expose a second oxide layer;

etching the second oxide layer to expose the SiGe layer; and

forming the emitter in a volume previously occupied by the sacrificial emitter.

12. The method of claim 1 wherein the masking material comprises photoresist.

13. A method of fabricating a bipolar transistor, the method comprising:

forming a sacrificial emitter over a base;

forming a first oxide layer over the sacrificial emitter;

forming a masking material over the sacrificial emitter such that a portion of the first oxide layer is exposed;

isotropically etching the first oxide layer to create an undercut under the masking material and fully expose a top portion of the sacrificial emitter; and

removing the sacrificial emitter.

14. The method of claim 13 wherein isotropically etching the first oxide layer comprises wet etching the first oxide layer.

15. The method of claim 13 wherein the base comprises silicon-germanium (SiGe).

16. The method of claim 13 wherein the sacrificial emitter comprises:

a polysilicon material over a second oxide layer.

17. The method of claim 13 further comprising:

after forming the sacrificial emitter but prior to forming the first oxide layer, implanting a dopant in an extrinsic base region.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2021
From: SPEARHEAD IP LLC
To: VIEWPOINT IP LLC
Reel/Frame 055063/0574 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 26, 2021
From: MONTEREY RESEARCH LLC
To: SPEARHEAD IP LLC
Reel/Frame 055029/0317 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →