Optoelectronic circuit employing a heterojunction thyristor device that performs high speed sampling

1. An optoelectronic circuit comprising:

a) a substrate;

b) a resonant cavity that is formed on said substrate and into which is injected an input optical signal; and

c) a heterojunction thyristor device, formed in said resonant cavity, that includes

i) an anode terminal and a cathode terminal;

ii) first and second channel regions disposed between said anode terminal and said cathode terminal, and

iii) an electrical input terminal and an electrical output terminal coupled to opposite ends of said first channel region,

wherein, in response to a light intensity level of said input optical signal corresponding to a predetermined ON condition, sufficient charge is generate in said second channel region to cause said heterojunction thyristor device to operate in an ON state whereby current flows between said anode terminal and said cathode terminal and said electrical input terminal is electrically coupled to said electrical output terminal, and

in response to a light intensity level of said input optical signal corresponding to a predetermined OFF condition, said heterojunction thyristor device operates in an OFF state whereby current does not flow between said anode terminal and said cathode terminal and said electrical input terminal is electrically isolated from said electrical output terminal.

2. An optoelectronic circuit according to claim 1 , wherein:

said input optical signal includes an optical clock signal comprising optical clock pulses that define sampling periods corresponding to bits of information.

3. An optoelectronic circuit according to claim 2 , further comprising:

a current source operably coupled to said second channel region that draws charge from said second channel region such that, upon termination of each given optical clock pulse, charge in said channel region is decreased below a holding charge such that said heterojunction thyristor device operates in said OFF state.

4. An optoelectronic circuit according to claim 1 , wherein:

said input optical signal includes an input digital optical signal that encodes bits of information, each bit representing an OFF logic level or an ON logic level.

5. An optoelectronic circuit according to claim 4 , wherein:

said input optical signal further includes an optical clock signal comprising optical clock pulses that define sampling periods corresponding to said bit of information.

6. An optoelectronic circuit according to claim 5 , further comprising:

a current source operably coupled to said second channel region that draws charge from said second channel region such that a given optical clock pulse alone induces a charge in said second channel region below a holding charge such that said heterojunction thyristor device operates in said OFF state.

7. An optoelectronic circuit according to claim 4 , wherein:

an electrical clock signal is injected into said second channel region, said electrical clock signal comprising electrical clock pulses that define sampling periods corresponding to said bits of information.

8. An optoelectronic circuit according to claim 7 , wherein:

said electrical clock signal contributes to said charge generated in said second channel region.

9. An optoelectronic circuit according to claim 7 , further comprising:

a current source operably coupled to said second channel region that draws charge from said second channel region such that a given electrical clock pulse alone induces a charge in said second channel region below a holding charge such that said heterojunction thyristor device operates in said OFF state.

10. An optoelectronic circuit according to claim 1 , wherein:

said heterojunction thyristor device is formed from a multilayer structure of group III-V materials.

11. An optoelectronic circuit according to claim 1 , wherein:

said heterojunction thyristor device is formed from a multilayer structure of strained silicon materials.

12. An optoelectronic circuit according to claim 1 , wherein:

said heterojunction thyristor device further comprises a p-channel FET transistor formed on said substrate and an n-channel FET transistor formed atop said p-channel FET transistor.

13. An optoelectronic circuit according to claim 12 , wherein:

wherein said p-channel FET transistor comprises a modulation dope p-type quantum well structure, and wherein said n-channel FET transistor comprises a modulation doped n-type quantum well structure.

14. An optoelectronic circuit according to claim 13 , wherein:

said first channel region comprises at least one p-type quantum well of said modulation doped p-type quantum well structure, and said second channel region comprises at least one n-type quantum well of said modulation doped n-type quantum well structure.

15. An optoelectronic circuit according to claim 13 , wherein:

said first channel region comprises at least one n-type quantum well of said modulation doped n-type quantum well structure, and said second channel region comprises at least one p-type quantum well of said modulation doped p-type quantum well structure.

16. An optoelectronic circuit according to claim 13 , wherein:

said p-channel FET transistor includes a bottom active layer operably coupled to said cathode terminal, and

said n-channel FET transistor includes a top active layer operably coupled to said anode terminal.

17. An optoelectronic circuit according to claim 16 , wherein:

said heterojunction thyristor device further comprises an ohmic contact layer, a metal layer for said anode terminal that is formed on said ohmic contact layer, and a plurality of p-type layers formed between said ohmic contact layer and said modulation doped n-type quantum well structure.

18. An optoelectronic circuit according to claim 1 , further comprising:

output circuitry, operably coupled to said electrical output terminal, that operates to hold an electrical signal derived from output of said electrical output terminal.

19. An optoelectronic circuit according to claim 18 , wherein:

said output circuitry outputs said electrical signal upon activation by an optical clock signal that includes optical clock pulses that occur subsequent to optic clock pulses supplied to said heterojunction thyristor device.

20. An optoelectronic circuit according to claim 19 , wherein:

said output circuitry is realized with another heterojunction thyristor device.

21. An optoelectronic circuit comprising:

a) a substrate;

b) a resonant cavity that is formed on said substrate;

c) a heterojunction thyristor device, formed in said resonant cavity, that includes

i) an anode terminal and a cathode terminal;

ii) first and second channel regions disposed between said anode terminal and said cathode terminal, and

iii) an electrical input terminal and an electrical output terminal coupled to opposite ends of said first channel region,

d) means for supplying an electrical control signal to said second channel region;

wherein, in response to said electrical control signal corresponding to a predetermined ON condition, charge is stored in said second channel region to cause said heterojunction thyristor device to operate in an ON state whereby current flows between said anode terminal and said cathode terminal and said electrical input terminal is electrically coupled to said electrical output terminal, and

in response to said electrical control signal corresponding to a predetermined OFF condition, said heterojunction thyristor device operates in an OFF state whereby current does not flow between said anode terminal and said cathode terminal and said electrical input terminal is electrically isolated from said electrical output terminal.

22. An optoelectronic circuit according to claim 21 , further comprising:

output circuitry, operably coupled to said electrical output terminal, that operates to hold an electrical signal derived from output of said electrical output terminal.

23. An optoelectronic circuit according to claim 22 , wherein:

said output circuitry outputs said electrical signal upon activation by an electrical clock signal that includes electrical clock pulses that occur subsequent to electrical clock pulses supplied to said heterojunction thyristor device.

24. An optoelectronic circuit according to claim 23 , wherein:

said output circuitry is realized with another heterojunction thyristor device.