Methods and apparatus for the hardware implementation of virtual concatenation and link capacity adjustment over SONET/SDH frames
View Patent ↗Methods and apparatus for the hardware implementation of virtual concatenation and link capacity adjustment over SONET/SDH frames include providing a state machine on chip with a SONET/SDH mapper and providing means whereby a plurality of members of a VCG can share the same state machine. The apparatus of the invention preferably includes a time wheel for granting access to the single state machine and memory for storing state information for each of the VCG members. According to the presently preferred embodiment, the invention is implemented on chip with an OC-3 Ethernet mapper. Up to eighty-four VCG members share the same state machine and memory is provided on the chip for maintaining the state information for eighty-four VCG members. Fifteen bits are used to store the state information for each VCG member in low order and seventeen bits are used to store the state information for each VCG member in high order. The presently preferred time wheel runs at 20 MHz.
1. A method for providing link capacity adjustment scheme (LCAS) for a virtual concatenation group (VCG) over SONET/SDH frames, comprising:
a) providing an LCAS finite state machine on a chip with a SONET/SDH mapper;
b) providing sharing means on the chip coupled to said state machine whereby a plurality of members of the VCG share the same state machine;
c) maintaining a plurality of registers, one for each member for storing the last state of each member; and
d) providing a status register for maintaining the present status of each member.
2. The method according to claim 1 , wherein:
the sharing means includes a time wheel.
3. The method according to claim 2 , wherein:
said time wheel generates AU3, TUG2, and TU2 indices.
4. The method according to claim 1 , further comprising:
e) providing a configuration register for maintaining the present configuration register for maintaining the present configuration of each member.
5. The method according to claim 1 , further comprising:
e) updating the status register with the state machine based on the last state of a member and network management commands.
6. The method according to claim 1 , wherein:
the plurality of members of the VCG comprises all members of the VCG.
7. The method according to claim 6 , wherein:
said step of providing a state machine comprises providing exactly one state machine.
8. The method according to claim 1 , wherein:
said plurality of registers and said status register are provided on the same chip as the state machine, the mapper, and the sharing means.
9. The method according to claim 1 , wherein:
the status register indicates whether the status of each member is “fixed”, “add”, “norm”, “eos”, “idle”, or “do not use”.
10. The method according to claim 4 , wherein: the configuration register indicates for each member “SQ”, “VCG”, and “Pool”.
11. An apparatus for providing link capacity adjustment scheme (LCAS) for a virtual concatenation group (VCG) over SONET/SDH frames, comprising:
a) an LCAS finite state machine on a chip;
b) sharing means on said chip coupled to said state machine whereby a plurality of members of a VCG share the same state machine;
c) a plurality of registers on said chip coupled to said sharing means, one register for each member for storing the last state of each member; and
d) a status register on said chip coupled to said sharing means for maintaining the present status of each member.
12. The apparatus according to claim 11 , wherein:
said sharing means includes a time wheel.
13. The apparatus according to claim 12 , wherein:
said time wheel generates AU3, TUG2, and TU2 indices.
14. The apparatus according to claim 12 , further comprising:
e) a configuration register coupled to said state machine for maintaining the present configuration of each member.
15. The apparatus according to claim 11 , wherein:
said status register is updated by the state machine based on the last state of a member and network management commands.
16. The apparatus according to claim 11 , wherein:
the plurality of members of the VCG comprises all members of the VCG.
17. The apparatus according to claim 11 , further comprising:
e) a SONET/SDH mapper coupled to said state machine, wherein
said mapper and said state machine are on the same chip.
18. The apparatus according to claim 11 , wherein:
said status register indicates whether the status of each member is “fixed”, “add”, “norm”, “eos”, “idle”, or “do not use”.
19. The apparatus according to claim 14 , further comprising wherein:
said configuration resister indicates for each member “SQ”, “VCG”, and “Pool”.
20. The apparatus according to claim 19 , further comprising wherein:
“Pool” includes an indication of one of “Global”, “Non-LCAS”, “LCAS-Idle”, and “LCAS-Add”.
21. An apparatus for providing link capacity adjustment scheme (LCAS) for a virtual concatenation group (VCG) over SONET/SDH frames, comprising:
a) an LCAS finite state machine on a chip;
b) sharing circuitry on said chip coupled to said state machine whereby a plurality of members of a VCG share the same state machine;
c) a plurality of registers on said chip coupled to said sharing circuitry, one register for each member for storing the last state of each member; and
d) a status register on said chip coupled to said sharing circuitry for maintaining the present status of each member.
22. The apparatus according to claim 21 , wherein:
said sharing circuitry includes a time wheel.
23. The apparatus according to claim 22 , wherein:
said time wheel generates AU3, TUG2, and TU2 indices.
24. The apparatus according to claim 23 , further comprising:
d) a configuration register coupled to said state machine for maintaining the present configuration of each member.
25. The apparatus according to claim 21 , wherein:
said status register is updated by the state machine based on the last state of a member and network management commands.
26. The apparatus according to claim 21 , wherein:
the plurality of members of the VCG comprises all members of the VCG.
27. The apparatus according to claim 21 , further comprising:
e) a SONET/SDH mapper coupled to said state machine, wherein
said mapper and said state machine are on the same chip.
28. The apparatus according to claim 21 , wherein:
said status register indicates whether the status of each member is “fixed”, “add”, “norm”, “eos”, “idle”, or “do not use”.
29. The apparatus according to claim 24 , wherein:
said configuration register indicates for each member “SQ”, “VCG”, and “Pool”.
30. The apparatus according to claim 29 , wherein:
“Pool” includes an indication of one of “Global”, “Non-LCAS”, “LCAS-Idle”, and “LCAS-Add”.