Instruction set reconciliation for heterogeneous symmetric-multiprocessor systems
View Patent ↗In a symmetric multiprocessing system using processors (DP 0 –DP 7 ) of different capabilities (instruction sets), a processor responds (S 11 ) to a query regarding its capabilities (instruction set) with its “active” capability, which is the intersection of its native capability and a common capability across processors determined (S 04 ) during a boot sequence ( 13 ). The querying application ( 29 ) can select (S 12 ) a program variant optimized for the active capability of the selected processor. If the application is subsequently subjected to a blind transfer to another processor, it is more likely than it would otherwise be (if the processors responded with their native capabilities) that the previously selected program variant runs without encountering unimplemented instructions.
1. A data processor implementing a native instruction set, said data processor comprising:
an execution unit for executing program instructions belonging to said native instruction set;
a capability register that:
during initialization indicates said native instruction set, and
in the event said data processor subsequently receives a common-capability value indicating a common instruction set, indicates an intersection of said sets.
2. A data processor as recited in claim 1 wherein said common instruction set is not equivalent to said native instruction set.
3. A data processor as recited in claim 1 wherein said common instruction set is not a subset of said native instruction set.
4. A data processor as recited in claim 1 further comprising:
a hardware representation of said native instruction set;
a writable register for receiving said common-capability value; and
means for computing said intersection.
5. In a method of initializing a multiprocessor system having processors with different instruction sets, the steps of:
polling the processors to determine the respective native instruction sets thereof;
determining a common instruction set that is a non-exhaustive subset of at least one of said native instruction sets; and
communicating said common instruction set to said processors.
6. A method as recited in claim 5 wherein said common instruction set is not a subset of at least one of said native instruction sets.
7. A method as recited in claim 5 further comprising step of, for each of said processors, calculating an active instruction set as a function of the respective native instruction set and said common instruction set.
8. A method as recited in claim 7 wherein, for each of said processors, said active instruction set is the intersection of the respective native instruction set and said common instruction set.
9. A method as recited in claim 8 wherein, for at least one of said processors, said common instruction set is not a subset of the respective native instruction set.
10. A method as recited in claim 5 wherein said common instruction set is the intersection of said native instruction sets.
11. A method as recited in claim 5 wherein said multiprocessor system is a partition of an incorporating multi-partition multi-processor system.
12. A method as recited in claim 5 wherein said processors are symmetrically configured.
13. A symmetric multiprocessor system comprising:
at least three symmetrically-configured data processors, each of said processors having a respective execution unit for executing program instructions belonging to a respective native instruction set, and a respective capability register that
during initialization indicates the respective native instruction set, and
in the event the respective data processor subsequently receives a common-capability value indicating a common instruction set for said symmetrically-configured processors, indicates a respective active instruction set that is a function of said common-instruction set and the respective native instruction set.
14. A symmetric multiprocessor system as recited in claim 13 wherein each of said respective active instruction sets is the intersection of said common instruction set and the respective native instruction set.
15. A symmetric multiprocessor system as recited in claim 13 wherein at least one of said respective active instruction sets is not the intersection of said common instruction set and the respective native instruction set.
16. A symmetric multiprocessor system as recited in claim 13 wherein said common instruction set is the intersection of said native instruction sets.
17. A symmetric multiprocessor system as recited in claim 13 wherein said common instruction set is not the intersection of said native instruction sets.