Method and apparatus for power routing in an integrated circuit
View Patent ↗A system and method for routing power between circuit blocks in an integrated circuit, such as macros and standard cells. A macro is wrapped in a relatively narrow power interface ring and placed in the integrated circuit such that the lower metal layers of the power interface ring are aligned and in direct contact with the power rails of a standard cell block. A power grid is formed above the macro and the upper metal layers of the power interface ring are coupled to the power grid. The upper power grid is tied either to an outer power bus or directly to power pins in the surrounding I/O ring. Data signals may be routed in the I/O ring space.
1. An integrated circuit having a plurality of conductive layers formed above device layers and comprising:
a first circuit block having circuitry components formed in the device layers and spaced power rails;
a second circuit block disposed adjacent the first block and surrounded by a power interface ring formed with power taps that directly abut the power rails of the adjacent first block to facilitate power routing between the first and second blocks; and
a power grid formed in one or more metal layers and connected to the power interface ring to facilitate power routing to the first and second blocks.
2. An integrated circuit as claimed in claim 1 , wherein the first circuit block is a standard cell block and the second circuit block is a macro.
3. An integrated circuit as claimed in claim 1 , wherein the power rails in the first circuit block are uniformly spaced and are formed in lower metal layers.
4. An integrated circuit as claimed in claim 1 , wherein the power interface ring extends from the device layers to upper metal layers.
5. An integrated circuit as claimed in claim 1 , wherein the power grid is formed in upper metal layers.
6. An integrated circuit as claimed in claim 1 , wherein the power grid is directly connected to power pins in a surrounding I/O ring, and wherein data signals are routed in the space typically occupied by the I/O ring.
7. An integrated circuit having lower conductive layers and upper conductive layers formed above device layers and comprising:
a standard cell block having circuitry components formed in the device layers and uniformly spaced power rails formed in the lower metal layers;
a macro disposed adjacent the standard cell block and surrounded by a power interface ring that extends from the device layers to the upper metal layers, wherein the power interface ring is formed with power taps that directly abut the power rails of the adjacent standard cell block in the lower metal layers to facilitate power routing between the macro and standard cell block; and
a power grid formed in the upper metal layers and being connected to the power interface ring to facilitate power routing to the standard cell block and macro.
8. An integrated circuit as claimed in claim 7 , wherein the power interface ring has a relatively narrow lateral width.
9. An integrated circuit as claimed in claim 8 , wherein the power interface ring has a lateral width in the range of approximately one to three microns.
10. An integrated circuit as claimed in claim 8 , wherein the power interface ring has a lateral width in the range of five to twenty times the minimum line size of the semiconductor process.
11. An integrated circuit as claimed in claim 7 , wherein the power interface ring is formed with active body ties that tie the lower metal layers of the power interface ring to the substrate layers or to diodes formed in the substrate layers.
12. An integrated circuit as claimed in claim 7 , wherein the power interface ring is formed with polycrystalline features.
13. An integrated circuit as claimed in claim 7 , wherein the upper metal layers of the power interface ring are formed with horizontal and vertical conductors that are tied to the upper power grid.
14. An integrated circuit as claimed in claim 7 , wherein the power grid formed in the upper metal layers covers the entire integrated circuit and is connected at its periphery to a power bus surrounding the integrated circuit.
15. An integrated circuit as claimed in claim 7 , wherein the power grid formed in the upper metal layers covers the entire integrated circuit and is directly connected at its periphery to power pins formed in an I/O ring at least partially surrounding the integrated circuit.
16. An integrated circuit as claimed in claim 15 , wherein signals are routed within the space typically occupied by the I/O ring.
17. An integrated circuit as claimed in claim 7 , wherein the power grid formed in the upper metal layers covers only the macro and not the entire integrated circuit.