Reverse-biased P/N wells isolating a CMOS inductor from the substrate
View Patent ↗A double well structure beneath an inductor to isolate it from the substrate. Contacts are provided for the deeper well and the substrate, to reverse bias the junction between the substrate and the deep well. In one embodiment, for a P-substrate, the deep well is an N-well, and the other well is a P-well. Both the N-well junction with the substrate, and the junction between the N-well and the P-well are reverse biased. This improves the quality factor of the inductor structure above the wells by reducing eddy currents. In one embodiment, the P-well is striped. The deeper N-well extends upward into the gaps between the stripes. The stripes will further reduce the amount of eddy current by adding a reverse biased sidewall junction to the eddy current path, further helping to increase the quality factor of the inductor.
1. An inductor structure comprising:
an inductor formed over a substrate;
a first well having a first type of polarity formed in said substrate between said substrate and said inductor;
a second well of a second type of polarity formed in said first well between said first well and said inductor; and
a first contact coupled to said first well to bias said first well wherein said second well is striped, with said first well extending upward into gaps between the stripes of said second well.
2. An inductor structure comprising:
an inductor formed over a substrate;
a first well having a first type of polarity formed in said substrate between said substrate and said inductor;
a second well of a second type of polarity formed in said first well between said first well and said inductor; and
a first contact coupled to said first well to bias said first well wherein said contact is polysilicon.
3. An inductor structure comprising:
an inductor formed over a substrate;
an n-well formed in said substrate between said substrate and said inductor;
a p-well formed in said n-well between said n-well and said inductor, wherein said p-well is striped, with said n-well extending upward into gaps between the stripes of said p-well;
a first contact coupled to said n-well to bias said n-well to a supply voltage; and
a second contact coupled to said substrate to bias said substrate to a lower voltage than said supply voltage, such that a junction between said n-well and said substrate is reverse biased.
4. The structure of claim 3 wherein said supply voltage is a highest available voltage on a chip, and said lower voltage is a lowest available voltage on said chip.
5. The structure of claim 3 further comprising a third contact connected to said p-well for biasing said p-well or leaving it floating.
6. The structure of claim 3 wherein said p-well has a higher resistivity than said substrate.