IP Library Granted Patent US 7,420,975
Granted Patent B1
US 7,420,975 · App. 10/327,524 · Granted Sep 2, 2008

Method and apparatus for a high-speed frame tagger

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,420,975
App. No.
10/327,524
Granted
Sep 2, 2008
Kind
B1
Abstract

In one embodiment, the invention is an apparatus. The apparatus includes a network processor interface suitable for coupling to a network processor. The apparatus further includes a central processor interface suitable for coupling to a central processor. The apparatus also includes a protocol determination logic block to determine a protocol type of data in a packet and steer the packet to either the central processor interface or the network processor interface based on the protocol type of data.

Claims (41)

1. A method, comprising:

extracting protocol information from a received packet within a framer;

comparing the protocol information in a first pass to predetermined values to produce a first result;

if the first result is negative, tagging the packet based on the first result;

if the first result is positive, comparing the protocol information in a second pass to predetermined values to produce a second result, the first and second results forming a set of results; and

tagging the packet based on the set of results.

2. The method of claim 1 , further comprising:

determining an offset within the packet at which the protocol information is located.

3. The method of claim 2 , further comprising:

skipping a number of bytes within the packet corresponding to the offset to find the protocol information.

4. The method of claim 1 , further comprising:

comparing the protocol information in a third pass to predetermined values to produce a third result of the set of results.

5. An apparatus, comprising:

a network processor interface suitable for coupling to a network processor;

a central processor interface suitable for coupling to a central processor;

a protocol determination logic block to determine a protocol type of data in a packet, wherein the protocol determination logic compares the protocol information in a first pass to predetermined values to procedure a first result and, if the first result is positive, compares the protocol information in a second pass to predetermined values to produce a second result, the first and second results forming a set of results; and

a tag select logic block to apply a tag to the packet indicating that the packet has an unknown protocol type if the first result is negative and if the first result is positive the packet should be sent to either the central processor interface or the network processor interface based on the set of results.

6. The apparatus of claim 5 , wherein the protocol logic block includes a protocol extractor to extract a location of protocol information of the packet.

7. The apparatus of claim 6 , wherein the protocol logic block includes a data register to store protocol information of the packet.

8. The apparatus of claim 7 , wherein the protocol logic block includes a comparator to compare contents of the data register to predetermined values.

9. The apparatus of claim 8 , wherein the protocol logic block includes a tag selector to select a tag based on a result of the comparator.

10. The apparatus of claim 9 , wherein the protocol logic block includes a protocol code memory to store the predetermined values.

11. The apparatus of claim 5 , wherein the network processor interface, central processor interface, and protocol determination logic block are included in a framer.

12. The apparatus of claim 11 , further comprising:

a central processor coupled to the central processor interface of the framer.

13. The apparatus of claim 12 , further comprising:

a network processor coupled to the network processor interface of the framer.

14. The apparatus of claim 13 , further comprising:

a physical link layer coupled to the framer.

15. The apparatus of claim 14 , further comprising:

a software stack coupled to the framer.

16. The apparatus of claim 15 , further comprising:

a host system coupled to the software stack and the network processor.

17. An apparatus:

means for extracting protocol information from a received packet within a framer;

means for comparing the protocol information in a first pass to predetermined values to produce a first result;

means for tagging the packet based on the first result if the first result is negative;

means for comparing the protocol information in a second pass to predetermined values to produce a second result if the first result is positive, the first and second results forming a set of results; and

means for tagging the packet based on the set of results.

18. The apparatus of claim 17 , further comprising:

means for determining an offset within the packet at which the protocol information may be found.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2023
From: INTELLECTUAL VENTURES ASSETS 162 LLC
To: WINTERSPRING IP LLC
Reel/Frame 064646/0876 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2023
From: WINTERSPRING IP LLC
To: WINTERSPRING DIGITAL LLC
Reel/Frame 064647/0045 →
SECURITY INTEREST Recorded Jul 21, 2021
From: WINTERSPRING IP LLC
To: INTELLECTUAL VENTURES ASSETS 169 LLC; INTELLECTUAL VENTURES ASSETS 162 LLC
Reel/Frame 056932/0665 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 11, 2021
From: CHEMTRON RESEARCH LLC
To: INTELLECTUAL VENTURES ASSETS 162 LLC
Reel/Frame 056514/0724 →
MERGER Recorded Oct 9, 2015
From: RUCTION CAPITAL LIMITED LIABILITY COMPANY
To: CHEMTRON RESEARCH LLC
Reel/Frame 036765/0929 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 23, 2012
From: CYPRESS SEMICONDUCTOR CORPORATION
To: RUCTION CAPITAL LIMITED LIABILITY COMPANY
Reel/Frame 027921/0579 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S STATE OF INCORPORATION PREVIOUSLY RECORDED ON REEL 013610 FRAME 0683. ASSIGNOR(S) HEREBY CONFIRMS THE SELL, ASSIGN, AND TRANSFER TO CYPRESS SEMICONDUCTOR CORPORATION OF THE ENTIRE RIGHT, TITLE, AND INTEREST. Recorded Feb 28, 2012
From: VASUDEVAN, VELAMUR KRISHNAMACHARI; ANNAYYA, DINESH
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 027779/0370 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 20, 2002
From: VASUDEVAN, VELAMUR KRISHNAMACHARI; ANNAYYA, DINESH
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 013610/0683 →