Enhancing data integrity and security in a processor-based system
View Patent ↗A smart card which includes a non-volatile read/write memory and a processor connected to the memory, and further configured to cause the processor to perform a method for enhancing data security and managing the contents of memory during periods when the computational power of the processor is underutilized. The method includes steps for determining if a command or character has been received, processing and/or responding to the command or character once received, implementing a security measure and/or managing memory, and performing a tamper protocol in response to detecting a security breach, all of which is performed while waiting to receive the next command or character.
1. A method of operating a device connected to a terminal, the method for taking advantage of wait cycles encountered between transmitted characters in a message received on a port, the method comprising:
receiving characters of a transmitted message from the terminal timed according to a reference clock;
operating a processor clock that is faster than the reference clock used for processing transactions with a terminal to which the device is connected;
processing each character of a message in a subset of processor clock cycles that correspond to one reference clock cycle such that the processor has wait cycles for each clock cycle of the reference clock;
performing a memory management task during the additional clock cycles encountered between characters transmitted as part of a message according to a port protocol, comprising:
executing a security measure to determine tampering associated with a memory during wait cycles encountered between characters transmitted as part of a message according to a port protocol, wherein the port protocol facilitates access to the memory; and
executing a tamper protocol in response to a determination of tampering to prevent an improper access to the memory.
2. The method of claim 1 , wherein managing the memory comprises accessing the memory to reduce fragmentation of data after receipt of a character of a command via the port protocol and prior to receiving a subsequent character via the port protocol.
3. The method of claim 1 , wherein the implementing a security measure comprises determining a key based upon a content of the memory.
4. The method of claim 3 , wherein determining a key comprises determining a checksum.
5. The method of claim 3 , wherein determining a key comprises encoding the content.
6. The method of claim 3 , wherein the implementing a security measure comprises verifying the content based upon the key after responding to a command received via the port protocol and prior to receiving a subsequent command via the port protocol.
7. The method of claim 3 , wherein the implementing a security measure comprises verifying the content based upon the key after receipt of a character of a command received via the port protocol and prior to receiving a subsequent character via the port protocol.
8. The method of claim 1 , wherein the implementing a security measure comprises comparing a checksum associated with a content of the memory against a reference checksum associated with the content.
9. The method of claim 1 , wherein the executing a tamper protocol comprises disabling the port protocol in response to the determination of tampering.
10. A data processing system configured to execute computer code having a plurality of transactions within the computer code and to take advantage of wait cycles between transmitted characters in a message received on a port, the data processing system comprising:
a memory to store private data;
a processor coupled with the memory and operating according to a processor clock;
a port coupled with the processor and operating according to a reference clock, wherein the reference clock is slower than the processor clock; and
having logic to cause the processor to
process each character of a message in a subset of processor clock cycles that correspond to one reference clock cycle such that the processor clock has wait cycles for each clock cycle of the reference clock;
perform a memory management task during the additional clock cycles encountered between characters transmitted as part of a message according to a port protocol, comprising logic to:
implement a security measure to determine tampering associated with the memory during the wait cycle encountered between characters transmitted as part of a message according to a port protocol, wherein the port protocol facilitates access to the memory; and
execute a tamper protocol in response to a determination of tampering to prevent an improper access to the memory.
11. The data processing system of claim 10 , wherein the logic to cause the processor to manage the memory comprises logic to access the memory to reduce fragmentation of data after receipt of a character of a command via the port protocol and prior to receiving a subsequent character of a command via the port protocol.
12. The data processing system of claim 10 , wherein the logic to cause the processor to implement a security measure comprises logic to determine a key based upon a content of the memory.
13. The data processing system of claim 12 , wherein the logic to determine a key comprises logic to determine a checksum.
14. The data processing system of claim 12 , wherein the logic to determine a key comprises logic to encode the content.
15. The data processing system of claim 12 , wherein the logic to cause the processor to implement a security measure comprises logic to verify the content based upon the key after responding to a command received via the port protocol and prior to receiving a subsequent command via the port protocol.
16. The data processing system of claim 12 , wherein the logic to cause the processor to implement a security measure comprises logic to verify the content based upon the key after receipt of a character of a command received via the port protocol and prior to receiving a subsequent character via the port protocol.
17. The data processing system of claim 10 , wherein the logic to cause the processor to implement a security measure comprises logic to compare a checksum associated with a content of the memory against a reference checksum associated with the content of the memory.
18. The data processing system of claim 10 , wherein the logic to cause the processor to execute a tamper protocol comprises logic to disable the port protocol in response to the determination of tampering.
19. A machine-readable medium storing a program of machine-readable instructions for causing a processor connected to a terminal to perform a method for taking advantage of wait cycles between transmitted characters in a message received on a port, the method comprising:
receiving characters of a transmitted message from the terminal timed according to a reference clock;
operating a processor clock that is faster than the reference clock used for processing transactions with a terminal to which the device is connected;
processing each character of a message in a subset of processor clock cycles that correspond to one reference clock cycle such that the processor clock has wait cycles for each clock cycle of the reference clock;
performing a memory management task during the additional clock cycles encountered between characters transmitted as part of a message according to a port protocol, comprising:
implementing a security measure to determine tampering associated with memory during a wait cycle encountered between characters transmitted as part of a message according to a port protocol, wherein the port protocol facilitates access to the memory; and
executing a tamper protocol in response to a determination of tampering to prevent an improper access to the memory.
20. The machine-readable medium of claim 19 , wherein managing the memory comprises accessing the memory to reduce fragmentation of data after receipt of a character of a command via the port protocol and prior to receiving a subsequent character via the port protocol.
21. The machine-readable medium of claim 19 , wherein the implementing a security measure comprises determining a key based upon a content of the memory.
22. The machine-readable medium of claim 21 , wherein determining a key comprises determining a checksum.
23. The machine-readable medium of claim 21 , wherein determining a key comprises encoding the content.
24. The machine-readable medium of claim 21 , wherein the implementing a security measure comprises verifying the content based upon the key after responding to a command received via the port protocol and prior to receiving a subsequent command via the port protocol.
25. The machine-readable medium of claim 21 , wherein the implementing a security measure comprises verifying the content based upon the key after receipt of a character of a command received via the port protocol and prior to receiving a subsequent character via the port protocol.
26. The machine-readable medium of claim 19 , wherein the implementing a security measure comprises comparing a checksum associated with a content of the memory against a reference checksum associated with the content of the memory.
27. The machine-readable medium of claim 19 , wherein the executing a tamper protocol comprises disabling the port protocol in response to the determination of tampering.