Capturing data and crossing clock domains in the absence of a free-running source clock
View Patent ↗Data, such as data received by a memory I/O from a memory unit in a DDR SDRAM system, is captured using a trigger signal, which may be a non free-running clock signal such as a DQS signal in a DDR SDRAM system, and is transferred to a host system, which may be part of an ASIC, using the host system's clock. The memory I/O includes a data capture register that latches the data received from the memory unit using DQS. The memory I/O also includes a FIFO buffer that latches the data output by the data capture register using a delayed version of DQS. A single edge of the delayed DQS is available to the FIFO for latching each set of data that corresponds to a single pulse of DQS. The FIFO transfers the data to the host system using the host system's clock, which represents a different clock domain than DQS.
1. A system comprising:
an interface unit;
a first module; and
a second module;
wherein the first module is coupled to the second module through the interface unit;
wherein the interface unit includes a data capture register coupled to a data buffer;
wherein the interface unit is operable to receive, from the second module, data and a first clock signal;
wherein the interface unit is further operable to generate a second clock signal by delaying the first clock signal;
wherein the data capture register is operable to latch the data using the first clock signal, resulting in registered data;
wherein the data buffer is operable to latch the registered data using the second clock signal, resulting in buffered data;
wherein the first clock signal is not a free-running clock signal;
wherein the data buffer is operable to provide the buffered data to the first module; and
wherein the first module and the second module operate in different clock domains.
2. The system of claim 1 , wherein the first module and the interface unit are embedded on the same integrated circuit.
3. The system of claim 1 , wherein, in delaying the first clock signal, the interface unit is operable to delay the first clock signal by a specified latency.
4. The system of claim 3 , wherein the specified latency is one-half cycle of the first clock.
5. The system of claim 3 , wherein the specified latency is very close to one-half cycle of the first clock.
6. The system of claim 3 ;
wherein the interface unit further includes a delay element; and
wherein the interface unit is operable to use the delay element in delaying the first clock signal.
7. The system of claim 1 , wherein the data capture register comprises a first set of flip-flops and a second set of flip-flops.
8. The system of claim 7 ;
wherein a first portion of the data is coupled to respective input ports of the first set of flip-flops; and
wherein the first set of flip-flops are operable to latch the first portion of the data on a leading edge of a pulse of the first clock.
9. The system of claim 7 ;
wherein a second portion of the data is coupled to respective input ports of the second set of flip-flops; and
wherein the second set of flip-flops are operable to latch the second portion of the data on a trailing edge of a pulse of the first clock.
10. The system of claim 7 , wherein the registered data is latched into the data buffer on a trailing edge of a pulse of the second clock.
11. The system of claim 1 ;
wherein the interface unit is further operable to receive a third clock signal from the first module; and
wherein the data buffer is operable to receive the third clock signal.
12. The system of claim 11 , wherein the data buffer is operable to transfer the buffered data to the first module using the third clock signal.
13. The system of claim 12 , wherein the data buffer is a FIFO.
14. The system of claim 13 , wherein the FIFO comprises:
a plurality of data registers;
a write-pointer generator block and a read-pointer generator block both coupled to a comparator block;
a data register enable block; and
a data register output select block;
wherein the registered data is coupled to respective input ports of each of the plurality of data registers;
wherein a respective output port of each of the plurality of data registers is coupled to a respective input port of the data register output select block;
wherein an output port of the read-pointer generator block is coupled to a select-input port of the data register output select block;
wherein the write-pointer generator block is coupled to the data register enable block; and
wherein each one of a plurality of output ports of the data register enable block is coupled to a respective enable input port of a respective data register of each of the plurality of data registers.
15. The system of claim 14 , wherein the comparator block is operable to generate a read-valid signal.
16. The system of claim 14 ;
wherein the write-pointer generator block is operable to receive the second clock signal; and
wherein operations of the write-pointer block are triggered by the second clock signal.
17. The system of claim 14 ;
wherein the read-pointer generator block is operable to receive the third clock signal; and
wherein operations of the read-pointer generator block are triggered by the third clock signal.
18. The system of claim 14 ;
wherein the FIFO further comprises a delay register block;
wherein an output port of the write-pointer generator block is coupled to a respective input port of the delay register block; and
wherein an output port of the delay register block is coupled to a respective input port of the comparator block.
19. A method for capturing data and transferring the data from a first clock domain to a second clock domain, the method comprising:
an interface unit receiving data;
the interface unit receiving a first clock signal;
the interface unit receiving a second clock signal from a host system;
the interface unit generating a third clock signal by operating on the first clock signal;
a data capture register inside the interface unit latching the data using the first clock signal, resulting in registered data;
a data buffer inside the interface unit latching the registered data using the third clock signal, resulting in buffered data; and
the data buffer using the second clock signal to transfer the buffered data to the host system;
wherein the first clock signal is not a free-running clock signal; and
wherein the first clock signal and the second clock signal represent two different clock domains.
20. The method of claim 19 , wherein said operating on the first clock signal comprises delaying the first clock signal by a specified latency.
21. The method of claim 20 , wherein the specified latency is one-half cycle of the first clock.
22. The method of claim 20 , wherein the specified latency is very close to one-half cycle of the first clock.
23. The method of claim 19 ;
wherein the data is received from a second system; and
wherein the first clock signal is received from the second system.
24. The method of claim 19 , wherein the data capture register comprises a first set of flip-flops and a second set of flip-flops.
25. The method of claim 24 , wherein said latching the data using the first clock signal comprises the first set of flip-flops latching a first portion of the data using a leading edge of a pulse of the first clock.
26. The method of claim 24 , wherein said latching the data using the first clock signal comprises the second set of flip-flops latching a second portion of the data using a trailing edge of a pulse of the first clock.
27. A system for capturing data and crossing clock domains, the system comprising:
a data capture register;
a data buffer; and
a clock modifier block;
wherein the data capture register and the clock modifier block are coupled to the data buffer;
wherein the data capture register is operable to receive read-data and a first clock signal, and latch the read-data using the first clock signal, resulting in registered read-data;
wherein the clock modifier block is operable to receive the first clock signal and generate a second clock signal by operating on the first clock signal;
wherein the data buffer is operable to receive the second clock signal and latch the registered read-data using the second clock signal, resulting in buffered read-data;
wherein the first clock signal is not a free-running clock signal;
wherein the data buffer is further operable to receive a third clock signal and transfer the buffered read-data to a receiving module coupled to the system, using the third clock signal;
wherein the receiving module provides the third clock signal; and
wherein the first clock signal and the second clock signal represent different clock domains.
28. The system of claim 27 , wherein the system is part of a Memory I/O.
29. The system of claim 28 , wherein a memory module provides the read-data and the first clock signal.
30. The system of claim 29 , wherein the memory module is a DDR SDRAM.
31. The system of claim 30 , wherein the first clock signal is a DQS signal.
32. The system of claim 27 , wherein the receiving module is a memory controller.
33. The system of claim 32 , herein the memory controller is a DDR SDRAM controller.
34. The system of claim 33 , herein the first clock signal is a DQS signal.
35. The system of claim 27 , wherein the system and the receiving module are embedded on the same integrated circuit.
36. The system of claim 27 , wherein the data buffer is a FIFO.
37. The system of claim 36 , herein the FIFO comprises:
a plurality of data registers;
a write-pointer generator block and a read-pointer generator block both coupled to a comparator block;
a data register enable block; and
a data register output select block;
wherein the registered data is coupled to respective input ports of each of the plurality of data registers;
wherein a respective output port of each of the plurality of data registers is coupled to a respective input port of the data register output select block;
wherein an output port of the read-pointer generator block is coupled to a select-input port of the data register output select block;
wherein the write-pointer generator block is coupled to the data register enable block; and
wherein each one of a plurality of output ports of the data register enable block is coupled to a respective enable input port of a respective data register of each of the plurality of data registers.
38. The system of claim 37 , herein the comparator block is operable to generate a read-valid signal.
39. The system of claim 37 ;
wherein the write-pointer generator block is operable to receive the second clock signal; and
wherein operations of the write-pointer block are triggered by the second clock signal.
40. The system of claim 37 ;
wherein the read-pointer generator block is operable to receive the third clock signal; and
wherein operations of the read-pointer generator block are triggered by the third clock signal.
41. The system of claim 37 ;
wherein the FIFO further comprises a delay register block;
wherein an output port of the write-pointer generator block is coupled to a respective input port of the delay register block; and
wherein an output port of the delay register block is coupled to a respective input port of the comparator block.