IP Library Granted Patent US 6,999,127
Granted Patent B2
US 6,999,127 · App. 10/327,881 · Granted Feb 14, 2006

Apparatus and method for image conversion and automatic error correction for digital television receiver

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Quick Facts
Patent No.
US 6,999,127
App. No.
10/327,881
Granted
Feb 14, 2006
Kind
B2
Abstract

Disclosed is an apparatus and method for image conversion and automatic error correction for a digital television receiver (TV) which can improve the picture quality by converting an image signal for a TV or PC that displays an image having an RGB format into an image signal of YPbPr for the digital TV and automatically correcting an error produced in the received image signal. The apparatus includes an image receiving and converting section for converting an image receiving and converting section for converting received RGB image data into image data of a digital TV format and rearranging parity bits and error information bits produced from the converted image data to form one image signal, a storage and image providing section for receiving the image signal from the image receiving and converting section, storing the image signal in a memory bank and providing the image signal so as to detect and correct an error produced in the image signal, and an error correcting and outputting section for receiving the image signal from the storage and image providing section, correcting the error by computing the parity bits and the error information bits from the original image data of the image signal, and interpolating the image to match a 16:9 aspect ratio for the digital TV.

Claims (38)

1. An apparatus for image conversion and automatic error correction for a digital television receiver (TV) comprising:

an image receiving and converting section for converting received RGB image data into image data of a digital TV format and rearranging parity bits and error information bits produced from the converted image data to form one image signal;

a storage and image providing section for receiving the image signal from the image receiving and converting section, storing the image signal in a memory bank and providing the image signal so as to detect and correct an error produced in the image signal; and

an error correcting and outputting section for receiving the image signal from the storage and image providing section, correcting the error by computing the parity bits and the error information bits from the original image data of the image signal, and interpolating the image to match a 16:9 aspect ratio for the digital TV.

2. The apparatus as claimed in claim 1 , wherein the image receiving and converting section comprises:

a digital image signal converter for converting the input RGB image data into the YPbPr image data to match the digital TV format by using a matrix conversion;

a parity-bit generation and data arrangement module for generating the parity bits by computing the image data if the image data is received from the digital image signal converter, generating the error information bits by computing the image data and the parity bits, and rearranging one image signal by the parity bits and the error information bits; and

a graphic address generator for generating an address signal for storing the image signal in the memory.

3. The apparatus as claimed in claim 1 , wherein the storage and image providing section comprises:

a memory controller for controlling storage and output of the image signal;

a memory bank for storing the image signal, and providing the image signal according to a signal inputted thereto; and

a signal arbitrator for selecting and outputting one among a plurality of input signals if a control signal is received.

4. The apparatus as claimed in claim 1 , wherein the error correcting and outputting section comprises:

a first-in first-out (FIFO) module for interface for receiving the image signal;

a parity-bit generator for receiving the image signal from the FIFO module and generating specified parity bits and error information bits from the image data;

an error-bit detection-correction module for correcting the error of the image signal by computing the parity bits and the error information bits generated from the parity-bit generator and the parity bits and the error information bits generated from the image receiving and converting section;

an interpolation processing module for receiving the corrected image signal from the error-bit detection-correction module and converting the image signal to match the aspect ratio of the digital TV;

a digital TV address generator for generating an address signal for outputting the error-corrected image signal to the digital TV; and

a sync generator for generating a sync signal to be outputted to the digital TV.

5. The apparatus as claimed in claim 4 , wherein the error-bit detection-correction module obtains parity values by computing the parity bits generated from the image receiving and converting section and the parity bits generated from the parity-bit generator, and correcting corresponding bits of the image data where the error is produced according to the parity values; and

wherein the error-bit detection-correction module detects the corresponding bits where many errors are produced by computing the error information bits generated from the image receiving and converting section and the error information bits generated from the parity-bit generator.

6. A method for image conversion and automatic error correction for a digital television receiver (TV) comprising:

a first step of receiving and converting image data of an RGB format into image data of an YPbPr format that is a digital TV format by a matrix conversion;

a second step of generating parity bits and error information bits from the image data and storing the parity bits and the error information bits;

a third step of reading the stored image signal through a memory controller;

a fourth step of regenerating parity bits and error information bits from the image data of the image signal;

a fifth step of obtaining parity values by computing the parity bits and the error information bits generated at the second step and the parity bits and the error information bits generated at the fourth step and correcting an error of a corresponding bit by the obtained parity values, and

a sixth step of outputting the image signal error-corrected at the fifth step to the digital TV.

7. The method as claimed in claim 6 , wherein the second step of generating and storing the parity bits and the error information bits from the image data comprises the steps of:

generating the parity bits by computing the image data;

generating the error information bits by computing again the image data and the parity bits; and

storing the image data, the parity bits, and the error information bits in the memory bank through the memory controller.

8. The method as claimed in claim 6 , wherein the fourth step of regenerating the parity bits and the error information bits from the image data of the image signal comprises the steps of:

generating the parity bits by computing the image data; and

generating the error information bits by computing again the image data and the parity bits.

9. The method as claimed in claim 6 , wherein the sixth step of outputting the image signal error-corrected at the fifth step to the digital TV comprises the steps of:

interpolating the image signal with an aspect ratio of the digital TV; and

generating the address and the sync signal to be outputted to the digital TV.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 12, 2018
From: UNILOC LUXEMBOURG S.A.
To: UNILOC 2017 LLC
Reel/Frame 046532/0088 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 14, 2018
From: PENDRAGON ELECTRONICS AND TELECOMMUNICATIONS RESEARCH LLC
To: UNILOC LUXEMBOURG S.A.
Reel/Frame 045338/0797 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 23, 2012
From: IPG ELECTRONICS 502 LIMITED; ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
To: PENDRAGON ELECTRONICS AND TELECOMMUNICATIONS RESEARCH LLC
Reel/Frame 028611/0643 →
ASSIGNMENT OF ONE HALF (1/2) OF ALL OF ASSIGNORS' RIGHT, TITLE AND INTEREST Recorded Nov 3, 2009
From: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
To: IPG ELECTRONICS 502 LIMITED
Reel/Frame 023456/0363 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 26, 2002
From: RYOO, DONG WAN; LEE, HYUNG JIK; LEE, JEUN WOO
To: ELECTRONICS AND TELECOMMUNICATION RESEARCH INSTITUTE
Reel/Frame 013618/0414 →