Granted Patent
Utility
US 6,746,945
· Confirmation No. 9117
METHOD OF FORMING A VIA HOLE IN A SEMICONDUCTOR DEVICE
Inventor:
Toshiyuki Orita
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2004-03-16 | IFEE |
Issue Fee Payment (PTO-85B) | 1 | View | |
| 2004-03-16 | IDS |
Information Disclosure Statement (IDS) Form (SB08) | 3 | View | |
| 2002-12-27 | TRNA |
Transmittal of New Application | 1 | View | |
| 2002-12-27 | A.PE |
Preliminary Amendment | 13 | View | |
| 2002-12-27 | SPEC |
Specification | 23 | View | |
| 2002-12-27 | CLM |
Claims | 7 | View | |
| 2002-12-27 | ABST |
Abstract | 1 | View | |
| 2002-12-27 | DRW |
Drawings-only black and white line drawings | 8 | View | |
| 2002-12-27 | OATH |
Oath or Declaration filed | 2 | View |
Inventors
Toshiyuki Orita
Tokyo, JAPAN
Attorneys & Agents of Record
Classification
USPC
438/597
H10W20/081
H10P50/283
Prosecution
- Examiner
- KESHAVAN, BELUR V
- Art Unit
- 2825
- Customer No.
- 23995
- Docket No.
- TAI 112C1
- Confirmation No.
- 9117
Publication
- Pub. No.
- US20030109123A1
- Pub. Date
- 2003-06-12
Patent Term Adjustment
-85days
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Quick Facts
- Patent No.
- US 6,746,945
- App. No.
- 10/329,794
- Filed
- 2002-12-27
- Granted
- 2004-06-08
- Pub. No.
- US20030109123A1
- Examiner
- KESHAVAN, BELUR V
- Art Unit
- 2825
- PTA
- -85 days
External Links