Semiconductor device and a method of manufacturing the same

1. A method of manufacturing a semiconductor device having an n-channel conductivity type field effect transistor and a p-channel conductivity type field effect transistor, each formed over a semiconductor substrate, comprising steps of:

(a) forming first sidewall spacers over a semiconductor region between each of gate electrodes of said n channel conductivity type and p channel conductivity type field effect transistors and an element isolation region of said semiconductor substrate in alignment with each of said gate electrodes;

(b) forming, over the surface of said semiconductor region, a metal semiconductor reacted layer in alignment with said first sidewall spacers;

(c) forming second sidewall spacers over said metal-semicondutor reacted layer in self-alignment with said first sidewall spacers;

(d) forming, over said n-channel conductivity type and p-channel conductivity type field effect transistor, a first insulating film for generating a tensile stress in a channel formation region of said n-channel conductivity type field effect transistor so as to cover gate electrodes of said transistors;

(e) selectively removing said first insulating film from the upper surface of said p-channel conductivity type field effect transistor by etching;

(f) forming, over said n-channel conductivity type and said p-channel conductivity type field effect transistors, a second insulating film for generating a compressive stress in a channel formation region of said p-channel conductivity type field effect transistor so as to cover the gate electrodes of said transistors; and

(g) selectively removing said second insulating film from the upper surface of said n-channel conductivity type field effect transistor,

wherein said second sidewall spacers have etching selectivity over said first insulating film.

2. A method according to claim 1 ,

wherein said step (e) is effected by isotropic etching.

3. A method according to claim 1 ,

wherein said first and second insulating films are each an insulating film made of a silicon nitride film for self-aligning contact.

4. A method of manufacturing a semiconductor device having an n-channel conductivity type field effect transistor and a p-channel conductivity type field effect transistor, each formed over a semiconductor substrate, comprising steps of:

(a) forming first sidewall spacers over a semiconductor region between each of gate electrodes of said n channel conductivity type and p channel conductivity type field effect transistors and an element isolation region of said semiconductor substrate in alignment with each of said gate electrodes;

(b) forming, over the surface of said semiconductor region, a metal-semiconductor reacted layer in alignment with said first sidewall spacers;

(c) forming second sidewall spacers over said metal-semicondutor reacted layers in self-alignment with said first sidewall spacers;

(d) forming, over said n-channel conductivity type and p-channel conductivity type field effect transistors, a first insulating film for generating a compressive stress in a channel formation region of said p-channel conductivity type field effect transistor so as to cover the gate electrodes of said transistors;

(e) selectively removing said first insulating film from the upper surface of said n-channel conductivity type field effect transistor by etching;

(f) forming, over said n-channel conductivity type and said p-channel conductivity type field effect transistors, a second insulating film for generating a tensile stress in a channel formation region of said n-channel conductivity type field effect transistor so as to cover the gate electrodes of said transistors; and

(g) selectively removing said second insulating film over the p-channel conductivity type field effect transistor,

wherein said second sidewall spacers have etching selectivity over said first insulating film.

5. A method of manufacturing a semiconductor device having an n-channel conductivity type field effect transistor and a p-channel conductivity type field effect transistor, each formed over a semiconductor substrate, comprising steps of:

(a) forming sidewall spacers which cover the sidewalls of each of gate electrodes of said n-channel conductivity type and p-channel conductivity type field effect transistors;

(b) forming a first insulating film which at least covers said gate electrode and a semiconductor region of said p-channel conductivity type field effect transistor;

(c) forming a second insulating film for generating a tensile stress in a channel formation region of said n-channel conductivity type field effect transistor which covers said n-channel conductivity type and p-channel conductivity type field effect transistors;

(d) selectively removing said second insulating film from the upper surface of said p-channel conductivity type field effect transistor by etching;

(e) forming a third insulating film for generating a compressive stress in a channel formation region of said p-channel conductivity type field effect transistor which covers said n-channel conductivity type and p-channel conductivity type field effect transistors; and

(f) selectively removing said third insulating film from the upper surface of said n-channel conductivity type field effect transistors,

wherein said first insulating film has etching selectivity over said second insulating film.

6. A method according to claim 5 , further comprising a step of forming source drain contact holes for said n-channel transistor and said p-channel transistor after said step (b) and (d).

7. A method according to claim 5 ,

wherein said first insulating film is a deposited film which covers said sidewall spacer of said p-channel conductivity type field effect transistor.

8. A method according to claim 5 ,

wherein said first insulating film is a deposited film which covers said sidewall spacer of said p-channel conductivity type field effect transistor, and

wherein a metal semiconductor reacted layer formed in alignment with said sidewall spacers is disposed over the surface of said semiconductor region.

9. A method according to claim 5 ,

wherein said first insulating film is a thermally oxidized film formed on said gate electrode and a semiconductor region of said p-channel conductivity type field effect transistor.

10. A method according to claim 5 ,

wherein said first insulating film is a thermally oxidized film formed on said gate electrode and a semiconductor region of said p-channel conductivity type field effect transistor.

11. A method according to claim 5 ,

wherein said step (d) is carried out by isotropic etching.

12. A method according to claim 5 ,

wherein said step (f) is carried out by isotropic etching.

13. A method according to claim 5 ,

wherein said insulating films are each a silicon nitride film for self-aligning contact.

14. A method according to claim 5 , further comprising a step of forming a fourth insulating film over said second insulating film after said step (c) but before said step (d),

said step (d) including a step of selectively removing said fourth insulating film from the upper surface of said p-channel conductivity type field effect transistor.

15. A method according to claim 5 ,

wherein said first insulating film is a deposited film which covers said sidewall spacer of said p-channel conductivity type field effect transistor, and

wherein said method further comprises removing said deposited film on the side of said p-channel conductivity type field effect transistor after said step (d) but before said step (e).

16. A method according to claim 5 ,

wherein said first insulating film is a deposited film which covers said sidewall spacer of said p-channel conductivity type field effect transistor, and

wherein, in said step (b), removing said deposited film on the side of said n-channel conductivity type field effect transistor after forming said deposited film over said n-channel conductivity type and p-channel conductivity type field effect transistors.

17. A method according to claim 7 ,

wherein said first insulating film is a deposited film which covers said sidewall spacer of said n-channel conductivity type field effect transistor, and

wherein said method further comprises removing said deposited film on the side of said n-channel conductivity type field effect transistor after said step (d) but prior to said step (e).

18. A method according to claim 7 ,

wherein said first insulating film is a deposited film which covers said sidewall spacer of said n-channel conductivity type field effect transistor, and

wherein, in said step (b), removing said deposited film on the side of said p-channel conductivity type field effect transistor after forming said deposited film over said n-channel conductivity type and p-channel conductivity type field effect transistors.

19. A method of manufacturing a semiconductor device having an n-channel conductivity type field effect transistor and a p-channel conductivity type field effect transistor, each formed over a semiconductor substrate, comprising steps of:

(a) forming sidewall spacers which cover the sidewalls of each of gate electrodes of said n-channel conductivity type and p-channel conductivity type field effect transistors;

(b) forming a first insulating film which at least covers said gate electrode and a semiconductor region of said n-channel conductivity type field effect transistor;

(c) forming a second insulating film for generating a compressive stress in a channel formation region of said p-channel conductivity type field effect transistor which covers said n-channel conductivity type and p-channel conductivity type field effect transistors;

(d) selectively removing said second insulating film from the upper surface of said n-channel conductivity type field effect transistor by etching;

(e) forming a third insulating film for generating a tensile stress in a channel formation region of said n-channel conductivity type field effect transistor which covers said n-channel conductivity type and p-channel conductivity type field effect transistors; and

(f) selectively removing said third insulating film from the upper surface of said p-channel conductivity type field effect transistor,

wherein said first insulating film has etching selectivity over said second insulating film.

20. A method according to claim 19 , further comprising a step of forming source drain contact holes for said n-channel transistor and said p-channel transistor after said steps (b) and (d).

21. A method according to claim 19 , further comprising the step of forming a fourth insulating film over said second insulating film after said step (c) but before said step (d),

said step (d) including a step of selectively removing said fourth insulating film from the upper surface of said n-channel conductivity type field effect transistor.