Data drive circuit for current writing type AMOEL display panel
View Patent ↗Data drive circuit for a current writing type AMOEL display panel including a plurality of current output channels, and a plurality of channel current generating circuits on respective current output channels for minimizing a difference of current levels occurred between the current output channels, each inclusive of one pair of transistors, a current generating part for generating a current of a small deviation proportional to square of a difference of threshold voltages of the one pair of the transistors, and a current mirror part for mirroring the current, and forwarding the mirrored current as a channel current for the channel, thereby minimizing a difference of current levels occurred between output channels, and driving the AMOEL display panel uniformly.
1. A data drive circuit for a current writing type AMOEL display panel comprising:
a plurality of current output channels; and
a plurality of channel current generating circuits on respective current output channels for minimizing a difference of current levels occurred between the current output channels, each including;
one pair of PMOS transistors having the same widths and lengths and a common gate terminal,
a first bias circuit connected to the common gate terminal of the pair of PMOS transistors for prevention of floating of the common gate terminal,
a first NMOS transistor for receiving an output current from the pair of PMOS transistors,
n (n+1, 2, 3, - - - ) second NMOS transistors connected to a gate terminal of the first NMOS transistor, each for forming a current mirror with the first NMOS transistor for mirroring the output current from the pair of the PMOS transistors, and
n PMOS transistors respectively connected to the n second NMOS transistors in series, wherein outputs of the n PMOS transistors are connected in parallel.
2. A data drive circuit as claimed in claim 1 , wherein, of the pair of the PMOS transistors, a first PMOS transistor has a body and a source connected together, which is in turn connected a first external bias circuit, and a second PMOS transistor has a body and a source connected together, which is in turn connected to a positive voltage power source.
3. A data drive circuit as claimed in claim 1 , wherein the bias circuit includes;
at least one NMOS transistor connected between the common gate and the ground in series, and
a second external bias used as a common gate voltage of the gates of the NMOS transistors.
4. A data drive circuit as claimed in claim 1 , wherein the n PMOS transistors control currents to the n second NMOS transistors in response to external n bit digital signals received as respective gate signals, to forward as respective channel currents.
5. A data drive circuit as claimed in claim 4 , wherein the respective channel currents are regulated to have a binary form of desired current levels by combination of the n-bit digital signals received at the n PMOS transistors.
6. A data drive circuit as claimed in claim 1 , wherein the n second NMOS transistors have widths and lengths fixed such that currents to the n second NMOS transistors are 2 a (a+0, 1, 2,- - - ) times of the output current from the pair of the PMOS transistors.