IP Library Granted Patent US 7,103,343
Granted Patent B2
US 7,103,343 · App. 10/337,050 · Granted Sep 5, 2006

Receiver, in particular for mobile radio

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Quick Facts
Patent No.
US 7,103,343
App. No.
10/337,050
Granted
Sep 5, 2006
Kind
B2
Abstract

A receiver, in particular for mobile radio, includes a receiver branch with a mixer, downstream of an analog/digital converter. A reference generator generates a reference clock, which is fed to the converters or PLL synthesizers of the mixer by integral multiplication or division. As a result, a particularly energy-saving and space-saving circuit configuration is realized, which has a low level of mutual interference between the signals and is suitable (in particular for Universal Mobile Telecommunication System, UMTS). In a preferred embodiment, the receiver is developed into a transceiver by providing a transmission path.

Claims (31)

1. A transceiver, comprising:

a first mixer having an input for receiving a reception signal and an output for tapping a first intermediate frequency signal;

a first phase locked loop for receiving a first mixer clock and connected to said first mixer;

an analog/digital converter connected to said output of said mixer for receiving a first converter clock;

a reference generator for generating a reference clock, the reference clock being an integral multiple of the first mixer clock, and the first converter clock being an integral multiple of the reference clock;

a second mixer having an input for receiving a second intermediate frequency signal and an output for tapping a transmission signal;

a second phase locked loop for receiving a second mixer clock and connected to said second mixer; and

a digital/analog converter connected to said input of said second mixer for receiving a second converter clock, the reference clock being an integral multiple of the second mixer clock, and the second converter clock being an integral multiple of the reference clock.

2. The transceiver according to claim 1 , wherein:

the first mixer clock is equal to the second mixer clock; and

the first converter clock is equal to the second converter clock.

3. The transceiver according to claim 1 , further comprising:

a first digital mixer connected downstream of said analog/digital converter;

a first interpolator connected downstream of said first digital mixer;

a second digital mixer connected upstream of said digital/analog converter; and

a sacond interpolator connected upstream of said second digital mixer.

4. The transceiver according to claim 3 , wherein each of said first and second interpolators has a plurality of sub-interpolators configured in series.

5. The transceiver according to claim 1 , wherein:

said analog/digital converter has a first digital filter; and

said digital/analog converter includes a second digital filter.

6. The transceiver according to claim 1 , wherein the reference clock has a clock frequency of substantially 13 MHz.

7. The transceiver according to claim 1 , wherein the reference clock has a clock frequency of substantially 40 MHz.

8. The transceiver according to claim 1 , wherein the converter clocks are substantially equal to the reference clock.

9. A transceiver for mobile radio, comprising:

a first mixer having an input for receiving a reception signal and an output for tapping a first intermediate frequency signal;

a first phase locked loop for receiving a first mixer clock and connected to said first mixer;

an analog/digital converter connected to said output of said mixer for receiving a first converter clock;

a reference generator for generating a reference clock, the reference clock being an integral multiple of the first mixer clock, and the first converter clock being an integral multiple of the reference clock;

a second mixer having an input for receiving a second intermediate frequency signal and an output for tapping a transmission signal;

a second phase locked loop for receiving a second mixer clock and connected to said second mixer; and

a digital/analog converter connected to said input of said second mixer for receiving a second converter clock, the reference clock being an integral multiple of the second mixer clock, and the second converter clock being an integral multiple of the reference clock.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2022
From: INTEL DEUTSCHLAND GMBH
To: INTEL CORPORATION
Reel/Frame 061356/0001 →
CHANGE OF NAME Recorded Nov 6, 2015
From: INTEL MOBILE COMMUNICATIONS GMBH
To: INTEL DEUTSCHLAND GMBH
Reel/Frame 037057/0061 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2012
From: INTEL MOBILE COMMUNICATIONS TECHNOLOGY GMBH
To: INTEL MOBILE COMMUNICATIONS GMBH
Reel/Frame 027556/0709 →