Method and apparatus for processing a complex instruction for execution and retirement

1. An instruction retirement apparatus, comprising:

an instruction decode unit arranged to decode a complex instruction that is not supported by hardware into a plurality of helper instructions, wherein the plurality of helper instructions are supported by hardware;

an execution unit arranged to execute the plurality of helper instructions;

a live instruction register arranged to indicate which of the plurality of helper instructions are alive; and

a complex instruction identification register arranged to maintain a complex instruction identification for the complex instruction, wherein the complex instruction identification register comprises a helper count register configured to indicate a number of helper instructions corresponding to the complex instruction,

wherein the instruction retirement apparatus comprises functionality to retire the complex instruction when the plurality of helper instructions have been executed without an exception, and wherein the complex instruction is retired if the number of helper instructions indicated by the helper count register matches a number of alive helper instructions corresponding to the complex instruction in the live instruction register.

2. The apparatus of claim 1 , wherein the live instruction register comprises a helper instruction register.

3. The apparatus of claim 1 , wherein the live instruction register comprises a retirement pointer register.

4. The apparatus of claim 1 , wherein the live instruction register comprises an instruction predecode register.

5. The apparatus of claim 1 , wherein the complex instruction identification register is arranged to maintain the complex instruction identification for each complex instruction dependent on a register location.

6. The apparatus of claim 1 , wherein the complex instruction identification register comprises an exception register.

7. The apparatus of claim 6 , wherein the execution unit is arranged to update the exception register after at least one of the plurality of helper instructions is executed.

8. The apparatus of claim 1 , wherein the complex instruction identification register comprises a complex instruction identification pointer register.

9. The apparatus of claim 1 , wherein the execution unit is arranged to execute at least two of the plurality of helper instructions concurrently.

10. The apparatus of claim 1 , wherein the instruction decode unit is arranged to support multiple strands.

11. A method for determining instruction retirement readiness, comprising:

decoding a complex instruction that is not supported by hardware into a plurality of helper instructions, wherein the plurality of helper instructions are supported by hardware;

executing the plurality of helper instructions;

indicating which of the plurality of helper instructions are alive using a live instruction register; and

maintaining a complex instruction identification for the complex instruction using, a complex instruction identification register,

wherein the complex instruction identification register comprises a helper count register configured to indicate a number of helper instructions corresponding to the complex instruction,

wherein the complex instruction is ready for retirement when the plurality of helper instructions have been executed without an exception and

wherein the complex instruction is retired if the number of helper instructions indicated by the helper count register matches a number of alive helper instructions corresponding to the complex instruction in the live instruction register.

12. The method of claim 11 , further comprising:

indicating whether an instruction is a helper instruction.

13. The method of claim 11 , further comprising:

indicating a first helper instruction of the plurality of helper instructions.

14. The method of claim 11 , further comprising:

maintaining an index into the live instruction register.

15. The method of claim 11 , wherein the maintaining is dependent on a register location.

16. The method of claim 11 , further comprising:

indicating an exception has occurred for at least one of the plurality of helper instructions.

17. The method of claim 16 , further comprising:

updating the exception dependent on the executing.

18. The method of claim 11 , further comprising:

maintaining an index into the complex instruction identification register.

19. The method of claim 11 , wherein the executing comprises executing at least two of the plurality of helper instructions concurrently.