Granted Patent B2

US 7,032,121 · App. 10/339,280 · Granted Apr 18, 2006

Abstract

Claims (86)

1. A method of generating a signal, comprising:

providing a clock signal having a frequency (f osc );

determining a common divisor between the clock frequency (f osc ) and a reference frequency (f r ), the signal having an output frequency (f o ) given by k*f r where k is an integer;

dividing the clock frequency (f osc ) by the common divisor to obtain a value N;

dividing the value N by the integer k to obtain a ratio R and a remainder given by r/k;

successively driving a counter using the clock signal to a count value of one of R and R+1, such that a fraction of times that the counter is driven to a count value of R is given by 1−r/k and a fraction of times that the counter is driven to a count value of R+1 is given by r/k; and

deriving the signal from an output of the counter.

2. The method of claim 1 , wherein successively driving the counter comprises:

initializing a sum to a value less than k;

repetitively performing the following at the signal frequency:

incrementing the sum by r;

determining if the sum is less than k;

setting the count value to R if the sum is less than k;

setting the count value to R+1 if the sum is not less than k; and

decrementing the sum by k if the sum is not less than k.

3. A method of generating a signal, comprising:

providing a clock signal having a frequency (f osc );

dividing the clock frequency (f osc ) by an output frequency (f o ) associated with the signal to obtain a ratio R and a remainder given by x/y;

successively driving a counter using the clock signal to a count value of one of R and R+1, such that a fraction of times that the counter is driven to a count value of R is given by 1-x/y and a fraction of times that the counter is driven to a count value of R+1 is given by x/y; and

deriving the signal from an output of the counter.

4. The method of claim 3 , wherein successively driving the counter comprises:

initializing a sum to a value less than y;

repetitively performing the following at the signal frequency:

incrementing the sum by x;

determining if the sum is less than y;

setting the count value to R if the sum is less than y;

setting the count value to R+1 if the sum is not less than y; and

decrementing the sum by y if the sum is not less than y.

5. A system for generating a signal, comprising:

means for providing a clock signal having a frequency (f osc );

means for determining a common divisor between the clock frequency (f osc ) and a reference frequency (f r ), the signal having an output frequency (f o ) given by k*f r where k is an integer;

means for dividing the clock frequency (f osc ) by the common divisor to obtain a value N;

means for dividing the value N by the integer k to obtain a ratio R and a remainder given by r/k;

means for successively driving a counter using the clock signal to a count value of one of R and R+1, such that a fraction of times that the counter is driven to a count value of R is given by 1−r/k and a fraction of times that the counter is driven to a count value of R+1 is given by r/k; and

means for deriving the signal from an output of the counter.

6. The system of claim 5 , wherein the means for successively driving the counter comprises:

means for initializing a sum to a value less than k;

means for incrementing the sum by r;

means for determining if the sum is less than k;

means for setting the count value to R if the sum is less than k;

means for setting the count value to R+1 if the sum is not less than k; and

means for decrementing the sum by k if the sum is not less than k;

wherein the means for initializing, the means for incrementing, the means for setting the count value to R, the means for setting the count value to R+1, and the means for decrementing operate at the signal frequency.

7. A system for generating a signal, comprising:

means for providing a clock signal having a frequency (f osc );

means for dividing the clock frequency (f osc ) by an output frequency (f o ) associated with the signal to obtain a ratio R and a remainder given by x/y; and

means for successively driving a counter using the clock signal to a count value of one of R and R+1, such that a fraction of times that the counter is driven to a count value of R is given by 1-x/y and a fraction of times that the counter is driven to a count value of R+1 is given by x/y; and

means for deriving the signal from an output of the counter.

8. The system of claim 7 , wherein the means for successively driving the counter comprises:

means for initializing a sum to a value less than y;

means for incrementing the sum by x;

means for determining if the sum is less than y;

means for setting the count value to R if the sum is less than y;

means for setting the count value to R+1 if the sum is not less than y; and

means for decrementing the sum by y if the sum is not less than y;

wherein the means for initializing, the means for incrementing, the means for setting the count value to R, the means for setting the count value to R+1, and the means for decrementing operate at the signal frequency.

9. A computer program product for generating a signal, comprising:

a computer readable storage medium having computer readable program code embodied therein, the computer readable program code comprising:

computer readable program code configured to provide a clock signal having a frequency (f osc );

computer readable program code configured to determine a common divisor between the clock frequency (f osc ) and a reference frequency (f r ), the signal having an output frequency (f o ) given by k*f r where k is an integer;

computer readable program code configured to divide the clock frequency (f osc ) by the common divisor to obtain a value N;

computer readable program code configured to divide the value N by the integer k to obtain a ratio R and a remainder given by r/k;

computer readable program code configured to successively drive a counter using the clock signal to a count value of one of R and R+1, such that a fraction of times that the counter is driven to a count value of R is given by 1−r/k and a fraction of times that the counter is driven to a count value of R+1 is given by r/k; and

computer readable program code configured to derive the signal from an output of the counter.

10. The computer program product of claim 9 , wherein the computer readable program code configured to successively drive the counter comprises:

computer readable program code configured to initialize a sum to a value less than k;

computer readable program code configured to increment the sum by r;

computer readable program code configured to determine if the sum is less than k;

computer readable program code configured to set the count value to R if the sum is less than k;

computer readable program code configured to set the count value to R+1 if the sum is not less than k; and

computer readable program code configured to decrement the sum by k if the sum is not less than k;

wherein the computer readable program code configured to initialize, the computer readable program code configured to increment, the computer readable program code configured to set the count value to R, the computer readable program code configured to set the count value to R+1, and the computer readable program code configured to decrement operate at the signal frequency.

11. A computer program product for generating a signal, comprising:

a computer readable storage medium having computer readable program code embodied therein, the computer readable program code comprising:

computer readable program code configured to provide a clock signal having a frequency (f osc );

computer readable program code configured to divide the clock frequency (f osc ) by an output frequency (f o ) associated with the signal to obtain a ratio R and a remainder given by x/y;

computer readable program code configured to successively drive a counter using the clock signal to a count value of one of R and R+1, such that a fraction of times that the counter is driven to a count value of R is given by 1-x/y and a fraction of times that the counter is driven to a count value of R+1 is given by x/y; and

computer readable program code configured to derive the signal from an output of the counter.

12. The computer program product of claim 11 , wherein the computer readable program code configured to successively drive the counter comprises:

computer readable program code configured to initialize a sum to a value less than y;

computer readable program code configured to increment the sum by x;

computer readable program code configured to determine if the sum is less than y;

computer readable program code configured to set the count value to R if the sum is less than y;

computer readable program code configured to set the count value to R+1 if the sum is not less than y; and

computer readable program code configured to decrement the sum by y if the sum is not less than y;

wherein the computer readable program code configured to initialize, the computer readable program code configured to increment, the computer readable program code configured to set the count value to R, the computer readable program code configured to set the count value to R+1, and the computer readable program code configured to decrement operate at the signal frequency.

Assignments (11)