Method of fabricating semiconductor devices employing at least one modulation doped quantum well structure and one or more etch stop layers for accurate contact formation

1. A method of fabricating a semiconductor device comprising the steps of:

providing a series of layers formed on a substrate, said layers including a first plurality of layers comprising n-type dopant material, a second plurality of layers that form a p-type modulation doped quantum well structure, and a third plurality of layers including an n-type modulation doped quantum well structure, wherein said first plurality of layers includes an n-type ohmic contact layer and a first etch stop layer for contacting said n-type ohmic contact layer;

performing an etching operation that automatically stops at said first etch stop layer;

removing remaining portions of said first etch stop layer to expose first areas of said n-type ohmic contact layer; and

depositing a first metal layer on said first areas of said n-type ohmic contact layer to form an electrode of said semiconductor device.

2. A method of fabricating a semiconductor device according to claim 1 , wherein:

said fist etch stop layer is made sufficiently thin to permit current tunneling.

3. A method of fabricating a semiconductor device according to claim 1 , wherein:

said series of layers further comprises a fourth plurality of layers comprising p-type dopant material, said fourth plurality of layers including a p-type ohmic contact layer.

4. A method of fabricating a semiconductor device according to claim 3 , wherein:

said fourth plurality of layers includes a second etch stop layer for contacting said n-type modulation doped quantum well structure.

5. A method of fabricating a semiconductor device according to claim 4 , further comprising:

performing an etching operation that automatically stops at said second etch stop layer;

removing remaining portions of said second etch stop layer to expose second areas of a layer thereunder;

implanting n-type ions in said second areas to form at least one n-type implant region that is operably coupled to said n-type modulation doped quantum well structure; and

depositing at least one metal layer on said n-type implant region to form an electrode of said semiconductor device that is operably coupled to said n-type modulation doped quantum well structure.

6. A method of fabricating a semiconductor device according to claim 4 , wherein:

said second etch stop layer is sufficiently thin to permit current tunneling.

7. A method of fabricating a semiconductor device according to claim 4 , wherein:

said series of layers further comprises

a first plurality of undoped spacer layers disposed between said first plurality of layers and said second plurality of layers,

a second plurality of undoped spacer layers disposed between said second plurality of layers and said third plurality of layers, and

a third plurality of undoped spacer layers disposed between said third plurality of layers and said fourth plurality of layers.

8. A method of fabricating a semiconductor device according to claim 7 , wherein:

said first plurality of undoped spacer layers and said third plurality of undoped spacer layers each include a thin capping layer.

9. A method of fabricating a semiconductor device according to claim 8 , further comprising:

performing an etching operation that exposes third areas of a layer between said n-type modulation doped quantum well structure and said p-type modulation doped quantum well structure;

implanting p-type ions in said third areas to form at least one p-type implant region that is operably coupled to said p-type modulation doped quantum well structure; and

depositing at least one metal layer on said p-type implant region to form an electrode of said semiconductor device that is operably coupled to said p-type modulation doped quantum well structure.

10. A method of fabricating a semiconductor device according to claim 1 , further comprising the steps of:

forming a plurality of distributed bragg reflector (DBR) mirror layers on said substrate.

11. A method of fabricating a semiconductor device according to claim 10 , wherein:

said plurality of distributed bragg reflector (DBR) mirror layers comprise layers of AlAs and GaAs.

12. A method of fabricating a semiconductor device according to claim 1 , wherein:

said second plurality of layers comprise at least one layer of undoped InGaAsN and at least one layer of undoped GaAs that form at least one quantum well.

13. A method of fabricating a semiconductor device according to claim 12 , wherein:

said second plurality of layers comprise at least one layer of AlGaAs of high p-type doping concentration to form a modulation doped layer for said at least one quantum well.

14. A method of fabricating a semiconductor device according to claim 1 , wherein:

said third plurality of layers comprise at least one layer of undoped InGaAsN and at least one layer of undoped GaAs that form at least one quantum well.

15. A method of fabricating a semiconductor device according to claim 14 , wherein:

said third plurality of layers comprise at least one layer of AlGaAs of high n-type doping concentration to form a modulation doped layer for said at least one quantum well.

16. A method of fabricating a semiconductor device according to claim 1 , wherein:

said first etch stop layer comprises AlAs, and said etching operations utilize a chlorine-based gas mixture that includes fluorine.

17. A method of fabricating a semiconductor device according to claim 4 , wherein:

said second etch stop layer comprises AlAs, and said etching operations utilize a chlorine-based gas mixture that includes fluorine.

18. A method of fabricating a semiconductor device according to claim 8 , wherein:

said thin capping layer comprises GaAs.

19. A method of fabricating a semiconductor device according to claim 3 , further comprising the steps of:

depositing a second metal layer that is electrically coupled to said p-type ohmic contact layer to form an anode electrode of a heterojunction thyristor device;

depositing at least one of a third metal layer and a fourth metal layer, said third metal layer electrically coupled to said n-type modulation doped quantum well structure to form at least one n-channel injector terminal electrode of said heterojunction thyristor device, and said fourth metal layer electrically coupled to said p-type modulation doped quantum well structure to form at least one p-channel injector terminal electrode of said heterojunction thyristor device; and

where said first metal layer forms a cathode terminal electrode of said heterojunction thyristor device.

20. A method of fabricating a semiconductor device according to claim 19 , further comprising the step of:

performing a first implant of n-type ions to form at least one n-type ion implant region that electrically couples said at least one n-channel injector terminal electrode to said n-type modulation doped quantum well structure.

21. A method of fabricating a semiconductor device according to claim 19 , further comprising the step of:

performing a second implant of p-type ions to form at least one p-type ion implant region that electrically couples said at least one p-channel injector terminal electrode to said p-type modulation doped quantum well structure.

22. A method of fabricating a semiconductor device according to claim 19 , further comprising the step of:

performing a first implant of n-type ions to form n-type implant regions that are disposed above said n-type modulation doped quantum well structure and that steer current into said n-type modulation doped quantum well structure.

23. A method of fabricating a semiconductor device according to claim 19 , wherein:

said series of layers is formed in a resonant cavity realized by a first plurality of distributed bragg reflector (DBR) mirror layers formed on said substrate and a second plurality of distributed bragg reflector (DBR) mirror layers formed on said series of layers.

24. A method of fabricating a semiconductor device according to claim 19 , wherein:

said second metal layer is deposited prior to said first, third and fourth metal layers.

25. A method of fabricating a semiconductor device comprising the steps of:

providing a series of layers formed on a substrate, said layers including a first plurality of layers including an p-type modulation doped quantum well structure, a second plurality of layers that form an n-type modulation doped quantum well structure, and a third plurality of layers including at least one layer comprising p-type dopant material, wherein said third plurality of layers includes a p-type ohmic contact layer and a first etch stop layer for contacting said n-type modulation doped quantum well structure;

depositing a first metal layer on said p-type ohmic contact layer to form a first electrode of said semiconductor device;

performing an etching operation that automatically stops at said first etch stop layer;

removing remaining portions of said first etch stop layer to expose first areas of a layer thereunder; and

depositing a second metal layer on said first areas to form at least one second electrode of said semiconductor device that is electrically coupled to said n-type modulation doped quantum well structure.

26. A method of fabricating a semiconductor device according to claim 25 , wherein:

said fist etch stop layer is made sufficiently thin to permit current tunneling.

27. A method of fabricating a semiconductor device according to claim 25 , further comprising the steps of:

performing a first implant of n-type ions in said first areas to form at least one n-type implant region that is electrically coupled to said n-type modulation doped quantum well structure; and

depositing said second metal layer on said at least one n-type implant region.

28. A method of fabricating a semiconductor device according to claim 25 , wherein:

said series of layers further comprises

a first plurality of undoped spacer layers disposed between said first plurality of layers and said second plurality of layers, and

a second plurality of undoped spacer layers disposed between said second plurality of layers and said third plurality of layers,

wherein said second plurality of undoped spacer layers include a thin capping layer.

29. A method of fabricating a semiconductor device according to claim 28 , further comprising the steps of:

performing an etching operation that exposes second areas between said n-type modulation doped structure and said p-type modulation doped structure;

depositing a third metal layer on said second areas to form a third electrode of said semiconductor device that is electrically coupled to said p-type modulation doped quantum well structure.

30. A method of fabricating a semiconductor device according to claim 29 , further comprising the steps of:

performing a second implant of p-type ions in said second areas to form at least one p-type implant region that is electrically coupled to said p-type modulation doped quantum well structure; and

depositing said third metal layer on said at least one p-type implant region.

31. A method of fabricating a semiconductor device according to claim 25 , further comprising the steps of:

forming a plurality of distributed bragg reflector (DBR) mirror layers on said substrate.

32. A method of fabricating a semiconductor device according to claim 25 , wherein:

said first etch stop layer comprises AlAs that functions as an etch stop during etching by a chlorine-based gas mixture that includes fluorine.

33. A method of fabricating a semiconductor device according to claim 25 , wherein:

said series of layers comprises group III–V materials.

34. A method of fabricating a semiconductor device according to claim 25 , wherein:

said series of layers comprises strained silicon heterostructures employing silicon-germanium (SiGe) layers.

35. A method of fabricating a semiconductor device according to claim 25 , further comprising the step of:

forming said series of layers utilizing molecular beam epitaxy.