Semiconductor memory apparatus simultaneously accessible via multi-ports
View Patent ↗A dual-port semiconductor memory apparatus constructed by a core circuit and a plurality of ports, different row blocks of which in the same column block of the core circuit are simultaneously accessible. Since each of the ports is provided with a global data bus, different row blocks of the same column block can be accessed via both ports by selectively activating a column line corresponding to a port and another column line corresponding to another port.
1. A semiconductor memory apparatus, comprising:
a first I/O port and a second I/O port;
a cell array circuit divided into a plurality of column blocks and a plurality of row blocks;
a first column line and a second column line corresponding to said first I/O port and said second I/O port, respectively;
a first global data bus and a second global data bus corresponding to said first I/O port and said second I/O port, respectively, said first global data bus and said second global data bus being provided to each one of the plurality of column blocks;
a first bus connection gate circuit that connects a sense amp of one of the plurality of row blocks selected in response to an access through said first I/O port, said sense amp being selected by said first column line, to said first global data bus; and
a second bus connection gate circuit that connects a sense amp of one of the plurality of row blocks selected in response to an access through said second I/O port, said sense amp being selected by said second column line, to said second global data bus.
2. The semiconductor memory apparatus as claimed in claim 1 , further comprising:
a first column gate and a second column gate corresponding to said first column line and said second column line, respectively, and said first column gate and said second column gate becoming conductive in response to an activation of the corresponding column line; and
a first local data bus and a second local data bus corresponding to said first I/O port and said second I/O port, respectively, said first local data bus and said second local data bus being connected to each sense amp through said first column gate and said second column gate, respectively;
wherein
said first local data bus is connected to said first global data bus through said first bus connection gate circuit; and
said second local data bus is connected to said second global data bus through said second bus connection gate circuit.
3. The semiconductor memory apparatus as claimed in claim 2 , further comprising:
a first bus connection signal generation circuit provided in a row block selected in response to an access through said first I/O port, said first bus connection signal generation circuit asserting a first bus connection signal; and
a second bus connection signal generation circuit provided in a row block selected in response to an access through said second I/O port, said second bus connection signal generation circuit asserting a second bus connection signal;
wherein
said first bus connection gate circuit becomes conductive depending on an asserted state of said first bus connection signal; and
said second bus connection gate circuit becomes conductive depending on an asserted state of said second bus connection signal.
4. The semiconductor memory apparatus as claimed in claim 3 , further comprising:
a first transistor provided between said first local data bus and each sense amp in series to said first column gate; and
a second transistor provided between said second local data bus and each sense amp in series to said second column gate;
wherein
said first transistor becomes conductive in response to an asserted state of said first bus connection signal; and
said second transistor becomes conductive in response to an asserted state of said second bus connection signal.
5. A semiconductor memory apparatus, comprising:
a first I/O port and a second I/O port;
a sense amp amplifying a data voltage on a bit line;
a first column line and a second column line corresponding to said first I/O port and said second I/O port, respectively;
a first column gate and a second column gate correspondingly provided to said first column line and said second column line, respectively, said first column gate and said second column gate becoming conductive in response to an activation of the corresponding column line;
a first local data bus and a second local data bus corresponding to said first I/O port and said second I/O port, respectively, said first local data bus and said second local data bus being connected to said sense amp via said first column gate and said second column gate, respectively;
a first global data bus and a second global data bus corresponding to said first I/O port and said second I/O port, respectively;
a first bus connection gate circuit connecting said first local data bus to said first global data bus; and
a second bus connection gate circuit connecting said second local data bus to said second global data bus.
6. The semiconductor memory apparatus as claimed in claim 5 , wherein
said first bus connection gate circuit connects said first local data bus to said first global data bus in a row block selected in response to an access via said first I/O port; and
said second bus connection gate circuit connects said second local data bus to said second global data bus in a row block selected in response to an access via said second I/O port.
7. The semiconductor memory apparatus as claimed in claim 6 , further comprising:
a first transistor provided between said first local data bus and said sense amp in series to said first column gate; and
a second transistor provided between said second local data bus and said sense amp in series to said second column gate;
wherein
said first transistor in a row block selected in response to an access via said first I/O port becomes conductive; and
said second transistor in a row block selected in response to an access via said second I/O port becomes conductive.